07-23-2015 10:30 AM
I have a legacy design done in Virtex4 that uses cascaded ISERDES to achieve a 10 bit parallel output from a single serial input. I want to move this design to a Kintex7. On page 153 of the ug471_7Series_SelectIO note it says the following:
"For a differential input, the master ISERDESE2 must be on the positive (_P pin) side of the
differential input pair. When the input is not differential, the input buffer associated with
the slave ISERDESE2 is not available, and so cascading cannot be used."
I don't have a differential input. I want to be sure I understand this note properly. It says I can't use ISERDESE2 cascading unless I use a diff pair?
07-24-2015 04:58 AM
07-24-2015 05:46 PM
I am not sure this is true (this actually looks like an error in the user guide).
Clearly, if you are using a single ended signal with ISERDES cascading, the single ended signal must be on the P side of the differential pair. What this statement (I think) should be saying is that if you use cascading, the input buffer of the slave is unavailaible (other than for use as the N side of a differential pair). If you are using a single ended signal, then the N side must be unused (you cannot use it for a different signal, even if you aren't going to use an ISERDES for that other signal).
You can try and open a webcase on this for clarification, but the easier solution is to try it in the tool. If this really is illegal, then the tools will flag it. Create a test design with a legal high speed clock (on a BUFIO and BUFR using proper division), your single ended signal, and the master and slave ISERDES. Be sure to route the outputs somewhere (maybe to 10 different output buffers). Take the design all the way through the tools including bitstream generation - if it makes it through the tools, then it is legal (and we can then work on getting the documentation clarified).