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eshopper
Observer
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Registered: ‎03-27-2018

Ibis model on Artix7 LVDS I/O unreliable ?

Customer is simulating LVDS pins on Artix7 with unreliable results (bad Signal integrity when Aritx is the receiving device).

The test topology used is

Topology.png

 

The signal integrity with a Cypress device as a clk  generator and any other receiver than Artix (here shown with SI53307) is ok,

However using IBIS model LVDS_25_HR_I_P/N produces results with non acceptable signal integrity, measured at the "Die" and the "pad" level.

(see attachments)

 

What is the cause of this effect?

 

J.Hofmann

 

SI_nicht_OK_Artix_LVDS_25_HR_I_at_die.png
SI_nicht_OK_Artix_LVDS_25_HR_I_at_pin.png
SI_OK_beliebiges_IC_mit_LVDS-Eingang.png
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gnarahar
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Registered: ‎07-23-2015

@eshopper Can you share their Artix 7 simulation schematic setup? 

Are they using the external 100 ohm termination resistor with the LVDS_25_HR_I_P/N model?

 

- Giri
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brimdavis
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Registered: ‎04-26-2012

@eshopper  "Customer is simulating LVDS pins on Artix7 with unreliable results (bad Signal integrity when Aritx is the receiving device)."

 

Is that same input terminator/bias network (R8,R77,R78,R79) also present in your LVDS_25_HR_I simulation of the FPGA input?

 

Since the CY2X013 is an LVDS device,  I would recommend eliminating the AC coupling caps and bias network and running your clock as a DC coupled LVDS signal.

 

If possible, use the internal FPGA differential LVDS termination. This is the LVDS_25_DT_HR_I variant of the IBIS model; you'll also need to use the appropriate DIFF_TERM attribute in your FPGA build to enable the internal termination.

 

Note that this internal terminator can only be used at certain VCCO supply voltages, 2.5V for 7-series HR pins, see AR43989. Otherwise, an external 100 ohm terminator can be used for LVDS at other VCCO supply voltages.

 

EDIT: If your 7-series HR I/O bank VCCO supply voltage is too low for LVDS inputs, then I'd suggest AC coupling into one of the low voltage differential standards with a split termination (e.g. for VCCO=1.35V, DIFF_SSTL135 with IN_TERM=UNTUNED_SPLIT_50, see UG471 v1.10 page 33), which will both terminate and bias the AC coupled input without needing any external resistors.

 

--------------------------

 Another possible issue is that many 'LVDS' devices, such as ADC's and clock generators, use a high impedance current source as an 'LVDS' driver without providing any back termination as required by the original LVDS standards.

 

I'm not familiar with your Cypress clock driver part, so I don't know if that's actually the case here.

 

 If so, when you drive a 350 ps edge from such a device into the ~10 pf (single ended) input capacitance of a typical FPGA, you can get horrible standing re-reflections for a clock waveform (and poor eyes for a data line) as the huge reflection from the FPGA input capacitance bounces off the high impedance driver and returns.

 

 This can be improved by adding back termination at the driver (at the cost of reduced signal swing unless the driver provides adjustable output current) , or by adding differential attenuation to damp out the reflections.

 

I put together a back-of-the-envelope LTSPICE model many years back (of a high-impedance LVDS ADC => FPGA) illustrating how adding back termination or attenuation addresses this problem:

  https://sites.google.com/site/fpgastuff/lvds_current.pdf

 

-Brian

 

p.s. This reflection issue also arises with PECL output clock generators (which have low output impedance); for those devices the back termination can be incorporated into the PECL Re emitter bias with an extra resistor:

  https://forums.xilinx.com/t5/Spartan-Family-FPGAs/Spartan-6-and-LVPECL/m-p/666867#M33358

 

p.p.s.

I would also note that there have historically been problems correctly modeling the internal terminations with certain versions of HyperLynx and certain Xilinx IBIS models (e.g. AR 37493 for Spartan6, Virtex4 DIFF_TERMs in HyperLynx V7.5 and earlier ), so I usually do a 'sanity check' simulation with a simple test waveform to verify that the termination is actually being modeled in the IBIS simulation.

sukhh
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Registered: ‎08-18-2016

Hello Brian,

 

I am working for the customer mentioned above - thank you for provided information.

 

The entire AC-coupling/DC-biasing-scheme is used since the clock is for a memory interface and must be in the same I/O bank, which has a VCCO of 1.35V. So, the termination network was present in the LVDS_25_HR_I simulation.


I wasn't aware about the possibility to terminate differential signals with the UNTUNED_SPLIT_50 termination. Is it correct that I can just drop R8,R77,R78,R79 and use the I/O standard DIFF_SSTL135_F_HR_IN50_P/N?

 

The linked PDF also provided quite some insight into the issue. I tried using back termination, but usefulness in our situation seems to be limited. The reflection in relation to the signal gets attenuated visibly, but the reflection still moves closer to the threshold levels.

 

In the attached screenshot you can see both variants (with and without back term) simulated for our actual layout, but with R77 and R8 removed, using the UNTUNED_SPLIT_50 termination. It looks like it will work, but I can't asses if the SI is "good enough" for reliable use. Can you provide advice on this question?

 

The relevant region of our layout is also attached to this post, with the back termination resistor added next to the oscillator.

 

Why does the AC701 eval board work reliably with something like 30-50 mm trace length, a similar oscillator and only a single termination resistor external to the FPGA? This configuration was the most problematic one in my attempts.

 

Best regards,

Alex

SI_DIFF_SSTL135_F_HR_IN50_with_and_without_back_term2.png
clocking_lvds2.png
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brimdavis
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Registered: ‎04-26-2012

@sukhh  "I wasn't aware about the possibility to terminate differential signals with the UNTUNED_SPLIT_50 termination. Is it correct that I can just drop R8,R77,R78,R79 and use the I/O standard DIFF_SSTL135_F_HR_IN50_P/N?"

 

 As far as I know, this method works just fine - I haven't done this specifically with an Artix-7, but I have done similar designs in other families using the split terminations for AC coupled differential signals. Just make sure that the IN_TERM attributes are added correctly to the .xdc file in the FPGA build.

 

I try to avoid the external termination/bias resistors within the BGA pattern whenever possible, for both layout ease and SI package stub effects.

 

>

> I tried using back termination, but usefulness in our situation seems to be limited.

> The reflection in relation to the signal gets attenuated visibly, but the reflection still moves closer to the threshold levels.

>

 Your clock signal looks *much* better to me with the back termination in terms of overshoot and reflections, although you've lost half the amplitude due to the double termination. ( As a test, try slowing the clock down 10x or so- the reflection damping effect and signal attenuation should be more visible with a longer clock period. )

 

 Are you sure those Vid thresholds are drawn correctly? IIRC the DIFF_SSTL135 Vid differential threshold is only 100 mV (Q-Q*) when using the differential input buffer, not 200 mV as shown by the dotted Vid threshold lines on your plot. EDIT1: nevermind that last sentence, I was reading the graph wrong.

 

 Increasing the back termination resistor (e.g. 100 to 200 ohms) will let you trade increased signal amplitude for reduced effectiveness of the back termination. You could also try increasing the IN_TERM value to UNTUNED_SPLIT_60. ( 200 ohm back term || 120 ohm Rdiff  => 75 ohm differential load when using IN_TERM_60; i.e. 3/4 the voltage swing you'd get compared to a single 100 ohm Rdiff.)

 

 EDIT2: For high impedance LVDS drivers *without* any drive current adjustment, the resistive matching approach is limited in how much extra attenuation you can add; a 3dB differential attenuator at the source (0.707 voltage drop), or equivalent loss for a back termination, is probably reasonable.

 

 My personal recommendation would be to remove your external resistor network, use the internal split termination, and leave a spot for the back termination on the board- you can then test in the lab with different termination values and compare the observed waveforms to those of your IBIS model to decide exactly what value to use.  (I often put a SATA or similar differential connector for testing on the board, connected to a clock-forwarding ODDR driving a differential output pair to perform clock jitter measurements in the system.)

 

>

> Why does the AC701 eval board work reliably with something like 30-50 mm trace length, a similar oscillator and

> only a single termination resistor external to the FPGA? This configuration was the most problematic one in my attempts.

>

I'm not familiar with that board, you'd have to ask Xilinx if they have any AC701 IBIS sims :)

 

-Brian

sukhh
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Registered: ‎08-18-2016

Hello Brian,

 

just wanted to share that I have followed your recommendations regarding the removal of the termination network and adding of a back termination resistor.

 

Even only using internal split termination was quite an improvement compared to the termination network.

 

Thanks for the guidance!

 

Alex

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