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chao_zhang
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Registered: ‎04-11-2014

If cascading IDELAY2 in Kintex7 will work?

I have a path from flip-flop to the IOB that needs programmable delay about 10ns. But the IDELAY2 can only provide 32 increment of 78ps at most, which means about  2.5ns, much lower than wanted. I am thinking if I can cascade several IDELAY2 to increase the delay. something like :

 

         IDELAY2                                 IDELAY2                           IDELAY2                          IDELAY2

[DATAIN -- DATAOUT] --> [DATAIN -- DATAOUT] --> [DATAIN -- DATAOUT] --> [DATAIN -- DATAOUT] ->IOB

 

I am new to xilinx FPGA, anyone knows if it is feasible ?

 

Thank you.

 

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vuppala
Xilinx Employee
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Registered: ‎04-16-2012

Hello @chao_zhang

 

You can cascade IDELAYE2s as mentioned in your post.

But the net from DATAOUT of one IDELAYE2 to DATAIN of other IDELAYE2 is routed through fabric routing since there is no dedicated routing.

 

Thanks,

Vinay

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mohsin_ch
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Registered: ‎05-25-2018

Sorry, what you mean by that? Fibre routing of FPGA. I am interested because i am also working on same ideas.

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pthakare
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Registered: ‎08-08-2017

Hi @mohsin_ch

 

There is no dedicate connection from the Data_out of first  IDELAYE2  to the Data_In of  next  IDELAYE2 in the cascade chain.

I.e  DATA_out is drive to the FPGA fabric and then to the DATA_IN of second IDELAYE2.

 

Also make sure that you are setting DELAY_SRC attribute of the all other IDELAYE2 in the cascade chain to DATA_IN as their data_in is driven from FPGA fabric.

 

For port and attribute description  refer 7 series selectIO user guide and for instantiation template refer 7 series libraries user guide

https://www.xilinx.com/support/documentation/user_guides/ug471_7Series_SelectIO.pdf  -> page 117

https://www.xilinx.com/support/documentation/sw_manuals/xilinx2018_2/ug953-vivado-7series-libraries.pdf   ->page345

 

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mohsin_ch
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Registered: ‎05-25-2018

Thanks for the reply. I got your point.

Please guide me how can i change the attributes? Because these are read only files.

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mohsin_ch
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Registered: ‎05-25-2018

I am describing in the detail. Picture is attached for reference.

 

Two IDELAYE2 are used in my design.

 

First IDELAYE2 Module:

1. No Serialization Factor.

2. Data_in_to_device[0:0] of first module is connected to data_in_from_pins[0:0] of Cascaded Module.

 

Second IDELAY2 Module:

1. Serialization Factor of 8.

2. data_in_to_device[7:0] connected to ILA for output.

 

During implementation, i got the following error message, "[Place 30-650] Non IO buffer mb_subsystem_i/RX_deSERIALIZER/inst/pins[0].fdre_in_inst{FDRE} is driving IDATAIN pin of IDELAY instance mb_subsystem_i/selectio_wiz_1/inst/pins[0].idelaye2_bus. This will lead to unroutable situation. IDATAIN pin of IDELAY instance should always get signal from IO buffer or GND."

 

Please help me out to resolve the issue.

 

DPA_IDELAY_CASCADED.PNG
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mohsin_ch
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Registered: ‎05-25-2018

I have change the DELAY_SRC attribute of the other IDELAYE2 in the cascade chain to DATA_IN, but it doesn't work.
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mohsin_ch
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Registered: ‎05-25-2018

Yes the problem is resolved by setting the DELAY_SRC attribute of the second IDELAY2 to DATAIN. One thing to remember is that Xilinx generated files are read only. First you edit the files and then open the project. Synthesize it. Check the RTL schematics and then run the implementation.

 

Thanks to Xilinx contributors.

 

 

 

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