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mrbietola
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Registered: ‎05-31-2012

Implementing Triple-Rate SDI Pass-Through Using an All-Digital VCXO Replacement Technique in Kintex 7

hi, i found the Xapp591 reference design, it's in Verilog and for Virtex-6

 

Is there a design example in VHDL and for kintex 7?

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bwiec
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Registered: ‎08-02-2011

Not exactly the same note, but have you seen this one?

http://www.xilinx.com/support/documentation/application_notes/xapp589-VCXO.pdf

www.xilinx.com
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mrbietola
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Registered: ‎05-31-2012

Thank you for your reply.

I saw that app but too generic for triple sdi.

Now i'm trying to take the pixco.ngc file from Xapp 591 and import it in the pass-through example project of Xapp 592.

I hope that even if the pixco.ngc was for Virtex 6 device, it will work on a Kintex 7.

 

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vve
Xilinx Employee
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Registered: ‎01-22-2008

The Virtex-6 netlist will not work in Kintex 7.

XAPP589 contains a netlist that can be used in xapp592.

 

Regards,

Vincent.

 

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mrbietola
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Registered: ‎05-31-2012

thank you i will try, i hope a complete design for triple rate SDI on Kintex 7 will be soon available

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mrbietola
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Registered: ‎05-31-2012

I did the VXCO on the kintex 7!

 

I found maybe a bug in the code in the drp controller (Xapp 592).   The drp controller, that should be used when rx_rate is changed to update the RXCDR_CFG attribute in the transceivers, i think  doesn't work (verified with chipscope).

In fact, the MSTR_STATE machine waits for a drprdy signal  high to start, but the signal is always low (it is driven high for 1 cycle by the transceiver after a write) and it stays there forever. 

 

 

Anyway, i can change from SD-SDI to HD-SDI but it takes so long time (10-15 seconds).

 

These are normal times of operation?

 

The drp controller is useful?

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jswang861224
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Registered: ‎08-06-2013

Hello! I'm new to Xilinx FPGA, recently I try to realize Triple-Rate SDI Pass-Through Using an All-Digital VCXO Replacement Technique in Kintex 7, and after my effort, HD_SDI has successfully passed through, but when using chipscope, the error_o signal is not 0, it often less then 50. When I change the input signal to SD_SDI, the output signal is not right, with some line on the picture, sometimes it shakes or change to black. And the video buffer is often full. It looks like the receive  clk is not locking to the transmit clk. Can you give me some advice?

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mrbietola
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Registered: ‎05-31-2012

 

You should change the PICXO parameters accordingly to the desired SDI mode. Look at xapp 591 in the example design what values were used.

I hope Xilinx release a new version of the xapp591 for the 7 series!

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