05-31-2018 12:54 AM
I'm trying to understand and implement clock gating to see how it affects power consumption in an example design .It's unclear to me if I have to add any logic myself, or if I simply have to check the "power opt design" in the implementation settings.
Checking this box seem to add logic gates which I presume is the clock enable logic, however it doesn't affect the power consumption at all. Is there something I'm missing?
05-31-2018 01:38 PM - edited 06-12-2018 10:36 AM
As with most RTL level power saving techniques, clock gating effectiveness is dependent on your design. So generally if your clock load is small clock gating will not save you much power. So say if you have a shallow design, clock gating will not be as effective as you think. On the other hand, if you have a design with large clock loads, for example, a BRAM heavy design, you will see a much bigger impact on power. I am guessing that your design is not sufficiently large enough to see a noticeable difference in power saving from intelligent clock gating or your design is already well optimized.
Have a read of WP370 if you haven't already. A lot of good info about intelligent clock gating.
06-12-2018 05:26 AM
Thanks for the response tenzinc,
My design has utilizes 45.5/50 BRAM which i consider to be pretty high. The clock stand for 10% of the whole power of the design, which is 0,078 W, which might not be considered alot. Should I not be seeing at least a decrease when activating intelligent clock gating?
06-12-2018 10:35 AM - edited 06-12-2018 10:35 AM
What device are you using? What Vivado version? Like I said generally for small, well optimized/pipelined designs clock gating will have little to no effect...
06-12-2018 11:58 PM
I'm using an Artix-7 XC7A35T-1, Vivado version 2018.1. I could see a decrease from 0,855 W to 0,851 W, which is something I guess.