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Participant herand
Participant
1,811 Views
Registered: ‎07-24-2017

Interior switching of LUT5 SRAM

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Hello,

 

I wouldd like to design a programmable delay line in a Zynq-7000 utilizing LUT5 blocks. Similar to some publications, I intend to modify the internal delay from the A1 - A6 inputs to the outputs O5/O6 by applying different static inputs in addition to a single feedthrough input. Theoretically, by selecting the correct input pins, I could modifiy the delay as different internal multiplexers are switched.

 

However, I have tried to find a descriptive insight into the switching scheme of a LUT5 but failed. UG474 and UG953 nicely describe the CLB and the routing of the LUTs, but show no insight to their switching.

 

Is there any documentation available, where I could see this swichting scheme?

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Scholar austin
Scholar
2,698 Views
Registered: ‎02-27-2008

Re: Interior switching of LUT5 SRAM

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https://patents.google.com/patent/US6400180B2/en?q=lut&assignee=xilinx&oq=xilinx+lut

 

For detailed information on how various structures operate, there is the user guides, such as ug474 for 7 series, or for more detailed information, you may look up one of our over 4,000 patents (as above).

 

The LUT is designed to be glitch-less for a change of one input.  The configuration (contents) of the 64 elements of the LUT are in the bitstream, which configures the type 2 configuration frames of the device.  One may choose to use a LUTRAM element, which will allow you to load dynamic data into the LUT cells.

 

The SRL uses master-slave arrangement of the 64 bits for a 32 bit shift register.

 

So, the Xilinx LUT is quite useful for all kinds of uses.  As a delay line, for synchronous data, the SRL is often useful (one can adjust the tap using the input address value from 0 to 31).

 

The LUT may also be used for asynchronous delay, but the carry chain is better for that, as it can provide a finer, and more continuous selection (although asynchronous design is not supported -- you are on your own there).

 

 

Austin Lesea
Principal Engineer
Xilinx San Jose
13 Replies
Scholar jmcclusk
Scholar
1,806 Views
Registered: ‎02-24-2014

Re: Interior switching of LUT5 SRAM

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I hate to disappoint you, but the internal LUT6 and LUT5 design is Xilinx proprietary.   It's a trade secret.   you can observe the external delay from the LUT inputs to the slice register inside Vivado,  but these input delays are completely static, and do not depend on the input values or programming pattern.   I can say that the I5 input on the LUT6 is almost certainly connected to a MUX control line, since it has a very small propagation delay, but anything beyond that is pure speculation.   You might be able to reverse engineer some of the timing by building a ring oscillator and observing the frequency shifts as you manipulate the inputs.   Doing this on many LUTS in series would magnify the effect, and make it easier to determine the average delay change...   However,  be aware that multi-element ring oscillators have overtone oscillation problems, so this might not work.

Don't forget to close a thread when possible by accepting a post as a solution.
Scholar austin
Scholar
2,699 Views
Registered: ‎02-27-2008

Re: Interior switching of LUT5 SRAM

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https://patents.google.com/patent/US6400180B2/en?q=lut&assignee=xilinx&oq=xilinx+lut

 

For detailed information on how various structures operate, there is the user guides, such as ug474 for 7 series, or for more detailed information, you may look up one of our over 4,000 patents (as above).

 

The LUT is designed to be glitch-less for a change of one input.  The configuration (contents) of the 64 elements of the LUT are in the bitstream, which configures the type 2 configuration frames of the device.  One may choose to use a LUTRAM element, which will allow you to load dynamic data into the LUT cells.

 

The SRL uses master-slave arrangement of the 64 bits for a 32 bit shift register.

 

So, the Xilinx LUT is quite useful for all kinds of uses.  As a delay line, for synchronous data, the SRL is often useful (one can adjust the tap using the input address value from 0 to 31).

 

The LUT may also be used for asynchronous delay, but the carry chain is better for that, as it can provide a finer, and more continuous selection (although asynchronous design is not supported -- you are on your own there).

 

 

Austin Lesea
Principal Engineer
Xilinx San Jose
Scholar austin
Scholar
1,789 Views
Registered: ‎02-27-2008

Re: Interior switching of LUT5 SRAM

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Incorrect,

 

A trade secret it is not:  it is patented.  For all to see, refer to the patents.

 

We do not wish to train competitors how to build FPGA devices.  But, we are happy to refer folks to the patents if that aids in their understanding and use of our products.

 

A trade secret is a dangerous form of intellectual property:  if someone else discovers it, and patents it, they now own it, and as we kept it secret, we no longer have the right to use it (we lose our intellectual property as we are punished for keeping it secret preventing improvements in the art).

 

So, trade secrets are few, and are carefully guarded, as they can get stolen, accidentally revealed, or even independently discovered.  We will not even reveal that a trade secret exists - after all, it is a secret.

Austin Lesea
Principal Engineer
Xilinx San Jose
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Participant herand
Participant
1,777 Views
Registered: ‎07-24-2017

Re: Interior switching of LUT5 SRAM

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Thank you both for your exhaustive answers.

 

What I inteded is to build ring-oscillators with a variable delay as in the publication titled "FPGA based True Random Number Generation using circuit metastability with Adaptive Feedback Control". There, the swiching design of a LUT3 in a Virtex 5 FGPA is shown and I wondered where to gather such a switching overview for a LUT5.

 

Hoped for a more simple version than a patent as they're usually hard to dig through but it will do the job.

 

Thank you.

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1,775 Views
Registered: ‎06-21-2017

Re: Interior switching of LUT5 SRAM

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1,760 Views
Registered: ‎06-21-2017

Re: Interior switching of LUT5 SRAM

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My bad.  The US is a First to Invent country, along with most of the world.  Been that way since 2013.

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Scholar jmcclusk
Scholar
1,736 Views
Registered: ‎02-24-2014

Re: Interior switching of LUT5 SRAM

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I have some advice on building random number generators...   Unless you really understand the technology and theory well, it's incredibly easy to create a circuit that is subtly flawed,  that *looks* like it's producing clean random numbers, but there's a bias or correlation that you have to dig hard to find.   The best ones I've found are the ones from Professor David B. Thomas, at the Imperial College, London.     I'm a big fan of his LUT-SR uniform random number generators, which have provided VHDL source code, and run incredibly fast.   How he concocted them is not so obvious, but the results speak for themselves.   I use them with a permutated adder stage to whiten the distribution, and I get very good results, even with sample numbers in the 10^14 range.    Having said that, they are NOT truly random, but are deterministic, and will give the same results every time when started with the same seed.  

 

If you genuinely need a TRNG,  then the best FPGA solution I've seen is Catalins Chaotic XOR Oscillator method.   If you need help coding it..  I've got some code lying around that can be adapted.

Don't forget to close a thread when possible by accepting a post as a solution.
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Participant herand
Participant
1,715 Views
Registered: ‎07-24-2017

Re: Interior switching of LUT5 SRAM

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Thanks for your offer to help, but actually I don't want to build a TRNG but use the ring oscillators as a PUF (Physical Unclonable Function). There, some of the bias you mentioned, which comes from the process variations, are wanted as they are the unclonable secret to be extracted, and some is unwanted like spatial variations and noise. Characterizing and reducing these unwanted influences is one of the major topics in the field right now.

 

PDL showed to be an excellent way of challenging these functions. However, in my case I just wanted to be sure that in my ring oscillators, the influence of the LUTs delay is not to marginal, therefore I wanted to select the switching scheme which could produce the longest internal delay.

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Participant herand
Participant
1,709 Views
Registered: ‎07-24-2017

Re: Interior switching of LUT5 SRAM

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I have found the switching scheme in another patent of Xilinx: Xilinx patent US7274211, Fig. 6 explains the switching scheme in the same way as I have seen it in other publications, showing which input controls which internal MUX and how IN6 controls the output of O6.

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Newbie bob.thing
Newbie
1,119 Views
Registered: ‎03-05-2018

Re: Interior switching of LUT5 SRAM

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Austin,

The figure below is from a Xilinx patent.

It shows the structure of a glitchless mux inside a LUT.

        Capture2.PNG

Your statement that no single input to a LUT can glitch the output implies that all the muxes in the LUT are glitchless.

If that is true, then no collection of inputs that individually do not change the output cannot collectively glitch the output.

For example, if a LUT is implementing an AND gate, if one of the inputs is low, then switching the other inputs, in any combination or sequence, cannot glitch the output.

Can you confirm this statement?

--Bob Thing

Northrop Grumman MS

Linthicum, MD

 

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Scholar austin
Scholar
1,109 Views
Registered: ‎02-27-2008

Re: Interior switching of LUT5 SRAM

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Bob,

 

I am not going to go that far, as glitch power is real.  As the 6 inputs to the LUT all arrive at different times the output rattles around (glitches back and forth until all 6 inputs stop changing).

 

As we ONLY support synchronous design, it really doesn't matter if the LUTs are glitchless or not on one input changing.  But, we do that to decrease the glitch power (as we can do something about it).  We cannot get all 6 inputs to arrive at once, so we have no control there.

 

 

Austin Lesea
Principal Engineer
Xilinx San Jose
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1,060 Views
Registered: ‎01-08-2012

Re: Interior switching of LUT5 SRAM

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"no single input to a LUT can glitch the output"

 

That statement is usually quoted as "no single input to a LUT can glitch the output provided that the other inputs to the LUT aren't changing."

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Scholar austin
Scholar
1,048 Views
Registered: ‎02-27-2008

Re: Interior switching of LUT5 SRAM

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Correct.

Austin Lesea
Principal Engineer
Xilinx San Jose
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