01-10-2017 09:15 AM
An FPGA offers huge potential to implement pulse width modulation (PWM) which can be used in conjunction with a simple smoothing circuit to perform D/A conversion. Pulse repetition frequency (PRF) and resolution can be whatever you want them to be providing the product of these two parameters falls within the clock frequency that the device can service (e.g. 8-bit input corresponds with 256 steps in duty cycle so a PRF of 1MHz would require a 256MHz clock). I've even heard of people using the high speed transceivers to implement extremely high PRF.
01-11-2017 01:08 PM
Its a bit old, but this might be of interest