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jhouee
Observer
Observer
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Registered: ‎11-27-2015

Internal Glitch within BUFG network Kintex7

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Hello,

After investigation in a heavy design (XC7K160T), our USB block is internally driving by a not gated 11Mhz via a BUFG.

Depending of the logic placement (very few changes) I am sure there is on more rising edge on this 11M clock but inside the BUFG clock network.

I  probe two signals functionally latched on 11MHz rising edge. Then we can see those two signals switching on rising edge but sometimes 15ns after falling edge of the 11M even if probing this 11M externally at the same time doesn’t show any glitch  !!!

So the extra rising edge is inside and may be created by reflected wave or cross talk …

Just changing a bit the implementation strategy option from default to explore fix the problem, and looking at the implemented design I don’t see that much difference !

I pushed more current on power supply to make sure of the stability but no impec.

Is that possible to get glicthes internally like that on clock network  ?

Can we tune the slow rate of a BUFG ?

Regards

Johann

 

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jhouee
Observer
Observer
689 Views
Registered: ‎11-27-2015

Hello,

We checked power is fine on 1V and  I/O power supply as well.

The thing is that one signal we probe which is supposed to be latched on the 11mhz can be latched at rising edge and at another fixed time in the same 11Mhz period once in a while.

Just adding those directive fix the issue, and this signal is always latched at rising edge only:

place_design -directive ExtraNetDelay_high

phys_opt_design -directive AggressiveExplore

route_design -directive Explore

So this is reason why i think something happen on the clock network.

I realy would like to understand what could happen

 

 

 

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drjohnsmith
Teacher
Teacher
702 Views
Registered: ‎07-09-2009

To answer the question, Nope,

The buf network will not generate a glitch, but if your feeding it a glitch, one will get through.

not certain on your conclusion from this test,

    you dont have a big glitch on the power at the chip do you ?

   I must admit, I could be proved wrong, but  I'd look else where for the bug,

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jhouee
Observer
Observer
690 Views
Registered: ‎11-27-2015

Hello,

We checked power is fine on 1V and  I/O power supply as well.

The thing is that one signal we probe which is supposed to be latched on the 11mhz can be latched at rising edge and at another fixed time in the same 11Mhz period once in a while.

Just adding those directive fix the issue, and this signal is always latched at rising edge only:

place_design -directive ExtraNetDelay_high

phys_opt_design -directive AggressiveExplore

route_design -directive Explore

So this is reason why i think something happen on the clock network.

I realy would like to understand what could happen

 

 

 

View solution in original post

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