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Registered: ‎10-12-2016

Internal Vref and Cascade DCI

Hi Friends, 

Can anyone explain about Internal Vref and Cascade DCI. I captured this below pic from vivado Floor planning. 

Internal Vref indicates what ?Internal Vref indicates what ?


NOTE: Any help or suggestions are highly appreciated. 


Thank You 

S Sampath

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Xilinx Employee
Xilinx Employee
Registered: ‎06-06-2018

Hi @ssampath,

DCI Cascade : If several I/O banks in the same I/O bank column are using DCI, and all
of those I/O banks use the same VRN/VRP resistor values, the internal VRN and VRP
nodes can be cascaded so that only one pair of pins for all of the I/O banks in the entire I/
O column is required to be connected to precision resistors. This option is called DCI

For more information please refer page 22 of UG471 (v1.10).

Internal Vref : The VREF for an I/O bank can be (optionally) generated inside the 7 series FPGA. Internal
generation removes the need to provide for a particular VREF supply rail on the printed
circuit board (PCB) and frees the multi-purpose VREF pins in a given I/O bank to be used
as normal I/O pins. Consider this alternative when the 7 series FPGA is the only device on
the board/system requiring a particular VREF voltage supply level, or if there is a shortage
of I/O pins in a given I/O bank. The internally generated VREF (INTERNAL_VREF) is
sourced from the VCCAUX. Each bank has a single VREF plane and each I/O bank can
therefore only have the optional INTERNAL_VREF set to a single voltage level for the
entire bank.

For more information please refer page 50 of UG471 (v1.10)


Deepak D N


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Deepak D N
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