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Registered: ‎02-13-2019

Internal and External Differential Terminations

Hi. I'm Jose.

The next, I think is mainly related to a PCB design doubt. I've been working on how to connect a SDRAM DDR3 and a ADC to a FPGA device. 

Here is this forummarkg@prosensing.com  helped me to clarify some important doubts I had about how to deal with voltages of the banks of the FPGA. Basically, there we talked about connecting signals to FPGA-banks with different  VCCO voltages and how to do that. For that there is no problem, my doubt is in the PCB connection.

(The voltage compatibilities and conditions to use the bank 33 to 1.5V and receive LVDS from ADC are fulfilled. the doubt is related with the nature of  the differential termination to use)

Basically for this doubt I have my interfaces in High Performance (HP) banks. 

In the Fig.1. is considered the first diagram of connection: In bank 33, the FPGA pins that receive LVDS signals coming from the ADC12 need to have an external differential termination (100 ohms); external because (As per forum ) the FPGA internal differential termination can not be used if the VCCO is not 1.8V (is 1.5V in this case) . At the other hand, for the bank 32, I can activate the 100-ohm termination internal to the FPGA (DIFF_TERM=TRUE) because VCCO = 1.8V. So, In bank 32 the terminations used are the FPGA internal terminations and in the bank 33 are external terminations that need to be added.

 

image (1).png

   Fig.1. Option 1 for the connection

 

In the Fig.2. is considered the second diagram of connection:  Here the bank 33 has the same consideration that was done above in the Fig.1.  But in this option 2, for the bank 32 it is considered that the needed terminations are externally added (despite it is possible to use the the internal termination ).

image.png

   Fig.2. Option 2 for the connection

So, here are my questions:

1- In the option-1, what would happen if in one bank the terminations used are the FPGA internals and in the other bank the used are put externally? that kind of "no-uniform" connection would be problematic?

2- The option 2 is drawn because of purpose of have a more "uniform"  connection for all the signals, i.e, all the terminations are external.

what are your opinions about these connections?

 

 

thank you.

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Registered: ‎03-31-2016

Re: Internal and External Differential Terminations

There should be no practical difference between internal and external termination from a functionality standpoint.  The internal will allow you to save board space at the cost of a tiny amount of extra power in the FPGA but you cannot then adjust the termination resistor value if you need to for signal integrity reasons, which you should not need to do and removes an easy probe or rework point.

Option 1 is great if you are tight on board space.

A lot of people would be more comfortable with 2 just to eliminate differences.  If you add the resistor pads for option 2 but do not populate them and use the internal termination of option 1 you can always rework the board to add the external resistor and change the bitstream to remove the internal termination.

 

BUT.....

 

One thing to be careful about is spreading an interface across multiple banks.  Depending on the clocking required you may have a lot of difficulty getting to work.  If the two banks connect to separate channels with separate clocks coming from the ADC you should be fine, if the data is one bank and the clock is on another it is going to be difficult depending on frequency and if the clock is free-running or not.  Be careful when selecting your clock pins, they have special requirements beyond what data pins require. 

I would strongly suggest getting a design with the full IO functionality to complete implementation before building a custom board.  You can use some other IPs or more basic internal logic if schedule is an issue but anything that touch an external pin should be completely developed at least until get to the intended internal data width and clocks.

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Registered: ‎01-22-2015

Re: Internal and External Differential Terminations

@jose09621 

I agree with advice that necare81 has given you.

Some more thoughts:

  1. I recall that you are using the XC7K160T.  Be sure to use the larger 676-pin packages which have bank 32 bonded out.

  2. I recall that you want your ADC to operate at 500MHz(250MHz DDR).  This is going to be very difficult and is pushing the limits of what will pass timing analysis with static capture.  Spreading the interface over two banks with different VCCOs makes things even more difficult.  Since banks 32 and 33 are vertically adjacent, you can start by trying the BUFIO+BUFMR (ChipSync) method for capturing the ADC data - as you and I discussed in your other post.  As necare81 reminds, it is very important to get all this working in Vivado before you build the board.

  3. As for external vs internal terminations, you are correct that LVDS internal terminations could be used when VCCO=1.8V – and not when VCCO=1.5V.  I agree with necare81 that using external terminations everywhere gives you flexibility and may help your interface pass timing since it helps you equalize all traces from the ADC to the FPGA.

  4. Modern PCB layout tools can usually help equalize the LVDS board traces (ie. make them look electrically equal in terms of delay and impedance).  Trace equalization will be important for both your ADC and SDRAM interfaces. For advice on board layout of high speed LVDS and terminations see Chapter 5 of UG483 and the following two links. 
    http://www.ti.com/lit/an/slla014a/slla014a.pdf?ts=1588768347194
    http://www.ti.com/lit/an/snla302/snla302.pdf?ts=1588770164047

  5. If static capture for the ADC interface cannot pass timing analysis, then dynamic capture methods are available.  Dynamic capture methods are complex. The basic idea is that the FPGA can, in real time, deskew the incoming data so that it is correctly captured.  XAPP1017 describes dynamic capture for a serial interface, although the method seems applicable to a parallel interface.

Mark

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Registered: ‎02-13-2019

Re: Internal and External Differential Terminations

Hi @necare81 , thank you for your answer:

1- what do you mean with "which you should not need to do"? why?

2- thanks for the option "If you add the resistor pads for option 2 but do not populate them..." it seems to be more reliable having a rework point as a backup option.

3- Regarding this "One thing to be careful about is spreading an interface across multiple banks..."  thanks for remind about this , also from the another forum that's been an useful advice (in addition to the the Vivado implementation with the functionality) which I've been thinking about since then, and for this case it can be done for the ADC (one channel in one bank and the other channel in other bank as you mentioned). But maybe if surge another interfaces I'll be facing the case of have spread interfaces across multiple banks. I'm working on the Vivado implementation, and still trying to undestand the constraints forum.

 

Hi markg@prosensing.com , 

1- Thanks Mark,fortunately that's the one I've been using in Vivado.

2- yes Mark,  I've seen some problems with timing working at 500MHz. I've been having into account the clocking architectures from the other forum, and also the needed constraints (which I'm still learning about). There is still work to do with it in Vivado because I don't have that completed yet.

3- Thanks for the guides about board layout and the one for dynamic capture. I'll get into all this information to know how to do this.

 

Thanks for your advice guys!

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Registered: ‎03-31-2016

Re: Internal and External Differential Terminations


@jose09621 wrote:

1- what do you mean with "which you should not need to do"? why?

 


I was referring to needing to use a different resistor value for the termination and that being very unlikely.  The value of the internal termination cannot be adjusted to help fix signal integrity issues but with a decent board manufacturer and PCB layout it shouldn't be an issue.

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Registered: ‎02-13-2019

Re: Internal and External Differential Terminations

@necare81 , thanks for clarify a bit more this to me.

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