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Registered: ‎07-23-2019

Is it a good idea to manipulate an output clock?

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I learnt (sometimes the hard way) not to play with FPGA clocks. "That's what the enable is for" I heard a number of times. And I stuck to that. Now, out of curiosity (as well as to clarify if someone is headed to the cliff edge or smarter than me), is it a good idea to control (stop and start with specific clock counts) outgoing clock signals from an Artix-7 at > 200 MHz?

 

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Teacher
Teacher
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Registered: ‎07-09-2009

Re: Is it a good idea to manipulate an output clock?

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Stopping clocks inside or outside the FPGA is used to save power,

But I guess you are not designing a big ultrascale+ desing, where the FPAG can disipate 100 plus watts, so the reasons to do it are low.

 

https://www.xilinx.com/support/documentation/application_notes/xapp790-7-series-clock-gating.pdf

 

As far as external signals from the fpga are concerned,

   the can be turned off also to save making noise , especialy in RF systems, but the disadvantages I have seen are, the far end can not then use a PLL / MMCM as the clock is intermitant, and its damed difficult to track a source of interferance if its intermitant .

 

<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>

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Scholar
Scholar
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Registered: ‎05-21-2015

Re: Is it a good idea to manipulate an output clock?

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@archangel-lightworks,

That depends upon the communication protocol you are working with.  I use SPI a lot, and definitely start and stop the clock with ever transaction.  I2C has a discontiuous clock.  etc.

Dan

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Registered: ‎07-23-2019

Re: Is it a good idea to manipulate an output clock?

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@dgisselq 

I2C, SPI at a few MHz should be fine, I believe. I'm talking of frequencies above 200 MHz, whatever the protocol, the question is whether, for example, one can send 17 of these clocks, then no clocks for 33 periods, then 25 more clocks, etc. (just arbitrary numbers to illustrate the case)

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Teacher
Teacher
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Registered: ‎07-09-2009

Re: Is it a good idea to manipulate an output clock?

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Stopping clocks inside or outside the FPGA is used to save power,

But I guess you are not designing a big ultrascale+ desing, where the FPAG can disipate 100 plus watts, so the reasons to do it are low.

 

https://www.xilinx.com/support/documentation/application_notes/xapp790-7-series-clock-gating.pdf

 

As far as external signals from the fpga are concerned,

   the can be turned off also to save making noise , especialy in RF systems, but the disadvantages I have seen are, the far end can not then use a PLL / MMCM as the clock is intermitant, and its damed difficult to track a source of interferance if its intermitant .

 

<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>

View solution in original post

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Registered: ‎07-23-2019

Re: Is it a good idea to manipulate an output clock?

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Interesting that "intelligent gating". It looks more oriented for internal gating than external. I will play with it when having some time. not yet sure it will allow cycle-by-cycle control with no downside

There is no need for a big ultrascale+ to save on power, just something for a cubesat with reduced power and there you are.

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