04-11-2019 06:45 AM - edited 04-11-2019 06:49 AM
Hi, I use to SP605 of Spartan6.
According to DS162_DC and Swtiching Characteristic, part of BUFGMUX, F_MAX, Global clock tree (BUFGMUX) Maximum clock tree is 400Mhz.
But, I want to use the 1057Mhz(DCM2PLL) at 'I' of BUFG(BUFGMUX).
Can I use it like this? and Is there any disadvantage?
04-11-2019 08:30 AM
Do i understnad ?
you want to use the internal DCM2PLL , running at 1000 plus MHz,
to send a 1000 plus MHz around the chip ?
04-11-2019 09:09 AM
-> Maximum Frequency of Global clock tree is 400Mhz,
It means that can't wire more than 400MHz of clocks to I-pin of BUFG (BUFGMUX)?
04-16-2019 02:17 AM
this is exactly what this means. You cannot use more than 400 MHz on any clock net. Even if the Input of the BUFGMUX would be OK with 1057 MHz the resulting output is going on a clock net which is limited to 400 MHz.
Besides, where exactly in DS162 is the 1057 MHz mentioned? If in any case u are refering to the VCXO frequency: this frequency is just used internally by the PLL and it is not possible to use this clock inside the FPGA. Besides this would violate pretty much every component switching limit there is.
Even the 400 MHz are very questionable, cuz I would doubt that you could actually design any useful circuit at such high frequencies. Remember, FPGAs are not as fast as ASICs, by far.