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Registered: ‎05-02-2016

Is negative Setup time possible?

Hello All,


I want to connect an LVDS data line to our Artix-7 Xilinx. There is an input clock, and an input data line. The schematic is as shown below.


In order to have a correct functionality of the system, I need the following timing relation to hold in the implemented design:


-1 < (DataPath - ClockPath) < 4


Where, the (DataPath-ClockPath) is the Setup time. So, in order to guide Vivado to fulfill the above relation, I have made following constraints:

create_clock -period 10.000 -name lvds_clk -waveform {0.000 5.000} [get_ports {clk_p}]

set_max_delay -from [get_ports {d_p d_n}] -to [get_pins lvds_reg/D] 4.00

set_min_delay -from [get_ports {d_p d_n}] -to [get_pins lvds_reg/D] -1.00


However, Vivado takes the set_min_delay as the hold time timing exception. How can I instruct Vivado to keep the setup time larger than -1?







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Registered: ‎01-23-2009

It is very hard to understand what you are asking for since you are asking for it in an "unusual" way...


You are trying to get some specific pin to pin timings out of the FPGA by describing that timing in terms of rather unusual constraints. This is sort of backwards. Normally one describes the system requirements to the FPGA using "normal" constraints, and then get the FPGA to meet this timing. Normal constraints mean using set_input_delay - not trying to do this set_max_delay and set_min_delay.


Furthermore, your nomenclature is confusing. You are trying to define a minimum delay and are then surprised by the fact that it is interpreting this as a hold time requirement - that is exactly what it is. You are trying to specify a min and a max timing - by definition, one will be the "worst" for the setup check and the other will be the "worst" for the hold check. There is no mechanism of doing anything else - you cannot set any constraint on the FPGA other than "pass setup" and "pass hold".


Next, your question of "can you have a -1ns setup" - the answer is yes, but you need to design an architecture that can handle this. Specifically, this means you need to have a fpga clocking mechanism that can delay your clock with respect to your data to accommodate this -1ns setup. Your design has an IDELAY on the data, but not the clock, so there is no way for the FPGA to meet this requirement.


Next, the clock mechanism you show (IBUFDS directly to clock input of the flip-flop) is basically illegal (or not real) - the tools will auto insert a clock buffer (BUFG) on this net. This results in pretty bad timing for an interface.


Finally, I am not sure what you expect the tools to do. Normally you place this capture flip-flop in the IOB. Done this way, you are in control of the timing of the interface, based on how you implement your clock insertion mechanism and your delay mechanisms. The timing constraints therefore become a mechanism of determining if the clock and delay mechanism you have implemented meet the requirements of the system. The tools do not adjust the timing of things like IDELAYs based on the constraints you apply...


So you need to take a step back and revisit your system. What does the system require? How do you capture those requirements as "normal" XDC constraints? How do you implement a clocking and delay structure that has a chance of meeting those system constraints? How do you adjust the timing of the programmable delays (IDELAY or MMCM phase delay) that will make the timing work given your constraints and clocking architecture.



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