12-10-2012 09:12 AM
I am using a Kinex-7 FPGA with many LVDS inputs without external terminations and I simulate them with Hyperlynx.
I have set the DIFF_TERM attribute to ON for some signals and OFF for other signals. But the simulation results are the same for both files even if the transmitter model is the same for all of the signals and the PCB traces are as equal as the layout permits.
How can I be sure the DIFF_TERM attribute value is reflected in the ibis file?
if they are not reflected in the ibis file
How can I simulate an on-die termination for LVDS signals with Hyperlynx?
12-10-2012 09:14 AM
You may check the resistors are selected by examining the IOB's in FPGA_Editor.
You may simulate them by adding a 100 ohm resistor in the simulation at the inputs.
12-10-2012 09:46 AM
You can check the IBIS [pin] section for the IO in question. If should reference the appropriate model with a _DT_ to stand for DIFF_TERM.
06-03-2013 12:14 AM - edited 06-03-2013 12:15 AM
I have the same problem. My Ibis model is done from Vivado, and named LVDS_25_DT_HR_I but the 100 Ohm termination does not seem to be included.
Does this model include any termination? Or should I just add a resistor in my simulation as suggested in the previous post? (This would actually not reflect the real situation... but is there a better way to do it?)