Issues with XADC PCB layout recommendations for Zynq 7000 SoC
I'm seeing some real issues with the XADC PCB layout recommendations provided in UG480 and XAPP554.
As you can see, REF3012 is a sensitive voltage reference that is an input (VREFP) to an ADC (powered at VCCADC pin) internal to Xilinx FPGA.
I understand the adding of a ferrite bead at the power rail is to try to get a clean power for REF3012 and VCCADC supply pin. However, there is a strong recommendation to add a ferrite bead at ground plane to generate a separate analog ground trace. Even more curious part is that they recommend us to route the VREFP and VREFN traces as tightly coupled differential pair shielded by VCCADC and GNDADC traces:
I find this dubious on two accounts:
 Say, I am routing all these four traces on a signal layer, and I have a continuous ground digital ground plane very adjacent to this signal layer. In such case, the VCCADC and the VREFP will use this digital ground plane as the return reference, not the VREFN trace (for VREFP) and GNDADC trace (for VCCADC). This is simply because energy (electromagnetic field) flows through a space of low impedance, and a digital ground plane (as a return conductor) provides a much lower transmission line impedance than the analog ground traces. Hence the most of the fields related to VCCADC power or VREFP signal will couple to the plane instead of the analog ground traces as supposed in the userguide and appnotes.
A simple experiment can clear this doubt: Just create a tightly edge-coupled differential pair in a stripline configuration in any simulator, and look at the field distribution. It will clear all the doubts.
 Secondly, VCCADC- GNDADC and VREFP-VREFN are not differential signals. There is no inverted version of signal flowing in through VREFN and GNDADC. They are just ground pins (more accurately return pins).