JTAG traces length matching for Zynq 7000 SoC

[binayak_shrestha]

Hi,

I am using Zynq 7000 SoC (xc7z045-2ffg900c). What are the length matching requirements for the JTAG signals:TCK, TDO, TDI, and TMS? I am planning to run them at 24 MHz clock.

Thanks n Regards,

Binayak

[markg@prosensing.com · Accepted solution]

@binayak_shrestha 

What are the length matching requirements for the JTAG signals .... at 24 MHz clock

Trace length-differences can be a problem when signal propagation delay through the length-difference is a significant part of the clock period.

The period of your 24MHz clock is 41.66ns.  The typical propagation delay for a signal through a circuit board trace is about 2ns/ft (6.56ns/m).  A 1cm length-difference is equivalent to (0.01m * 6.56ns/m = 0.0656ns) which is only 100*0.0656/41.66 = 0.16% of your clock period. 

So, at a clock speed of 24MHz, if you keep the JTAG signal trace length-differences to less than 1cm then the JTAG interface should work properly.

Please also read the "Signal Integrity" section starting on page 28 of UG593.

Cheers,
Mark

[joancab]

Besides the very educated answer from markg@prosensing.com , I would advise to have a length matching of 1-2 mm that is not difficult to achieve and will allow higher speeds if you ever need them.

[binayak_shrestha]

Thanks Mark and Joan for the help.

Regards,

Binayak