cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
Highlighted
Contributor
Contributor
6,339 Views
Registered: ‎09-04-2013

Jtag chain design with Virtex 7 and CoolRunner CPLD

Jump to solution
Hi, i am designing a schematic targeting at xc7xc330t. A coolrunner cpld is also used for level translating with other asics.

i have gone through many app notes and userguides, but still have some unsolved questions:

1) can i connect their jtag configuration pins in a chain to configure them together? (i am using vivado for fpga design, it seem that cpld is not supported by vivado. Does it mean i have to go back to ISE?)

2) if 1) is true, is it necesary to use level translators for jtag port connection between V7 and CPLD? (or, does coolrunnerII support 1.8v jtag configration?)
Tags (1)
0 Kudos
1 Solution

Accepted Solutions
Highlighted
Xilinx Employee
Xilinx Employee
8,475 Views
Registered: ‎07-31-2012

Hi,

 

Answering your questions.

 

1) can i connect their jtag configuration pins in a chain to configure them together? (i am using vivado for fpga design, it seem that cpld is not supported by vivado. Does it mean i have to go back to ISE?)

 

 Yes, you should be able to connect both the devices in chain using JTAG connections. The Vivado only supports the 7 series Xilinx Devices for generation of bitstream. You can generate a bitstream separately for xc7xc330t using Vivado and for the CPLD using ISE. Now you can use these both bitfiles in any Impact tool to generate an SVF file for JTAG programming. Hope this makes it clear.

 

2) if 1) is true, is it necesary to use level translators for jtag port connection between V7 and CPLD? (or, does coolrunnerII support 1.8v jtag configration?)

 

Yes, you can connect the V7 and CPLD devices in the JTAG chain. The coolrunner CPLD has a 1.8v JTAG interface. Check this CPLD overview user guide and search for JTAG - http://www.xilinx.com/support/documentation/data_sheets/ds093.pdf.  Based on JTAV voltage level in the V7 DEVICE, you need to use level translators.

 

However before doing that i would suggest you to read through the below brief documents on JTAG devices in chain

 

1) JTAG ISP - http://www.xilinx.com/support/documentation/application_notes/xapp104.pdf

2) Pg 43 of this user guide - http://www.xilinx.com/support/sw_manuals/2_1i/download/jtag.pdf

 

 

 

Thanks,
Anirudh

PS: Please MARK this as an answer in case it helped resolve your query.Give kudos in case the post guided you to a solution.

View solution in original post

5 Replies
Highlighted
Xilinx Employee
Xilinx Employee
8,476 Views
Registered: ‎07-31-2012

Hi,

 

Answering your questions.

 

1) can i connect their jtag configuration pins in a chain to configure them together? (i am using vivado for fpga design, it seem that cpld is not supported by vivado. Does it mean i have to go back to ISE?)

 

 Yes, you should be able to connect both the devices in chain using JTAG connections. The Vivado only supports the 7 series Xilinx Devices for generation of bitstream. You can generate a bitstream separately for xc7xc330t using Vivado and for the CPLD using ISE. Now you can use these both bitfiles in any Impact tool to generate an SVF file for JTAG programming. Hope this makes it clear.

 

2) if 1) is true, is it necesary to use level translators for jtag port connection between V7 and CPLD? (or, does coolrunnerII support 1.8v jtag configration?)

 

Yes, you can connect the V7 and CPLD devices in the JTAG chain. The coolrunner CPLD has a 1.8v JTAG interface. Check this CPLD overview user guide and search for JTAG - http://www.xilinx.com/support/documentation/data_sheets/ds093.pdf.  Based on JTAV voltage level in the V7 DEVICE, you need to use level translators.

 

However before doing that i would suggest you to read through the below brief documents on JTAG devices in chain

 

1) JTAG ISP - http://www.xilinx.com/support/documentation/application_notes/xapp104.pdf

2) Pg 43 of this user guide - http://www.xilinx.com/support/sw_manuals/2_1i/download/jtag.pdf

 

 

 

Thanks,
Anirudh

PS: Please MARK this as an answer in case it helped resolve your query.Give kudos in case the post guided you to a solution.

View solution in original post

Highlighted
Xilinx Employee
Xilinx Employee
6,312 Views
Registered: ‎08-01-2012

JTAG port has wide range of voltage support for many FPGA'S and CPLD'S. Please verify respective data sheets. There is a chance that  you may not need level translaters.

________________________________________________

Please mark this post as an "Accept as solution" in case if it helped to resolve your query. So that it will help to other forum users to directly refer to the answer.

Give kudos to this post in case if you think the information is useful and reply oriented.

Highlighted
Contributor
Contributor
6,273 Views
Registered: ‎09-04-2013
Thanks! Two more questions:

The 7series FPGA userguide recommends using buffers to keep the quality of TCK and TMS when they are distributed to multiple devices in a JTAG chain.

1) When should I buffer the critical signal? Commonly, buffers are used when the number of devices exceeds THREE. Does other criteria exsits(such as PCB layout, noise and trace length. etc)?

2) KC705 evaluation board does not use level translator when connecting K7's jtag pin(2.5V) to Diligent USB-JTAG IC and JTAG header(3.3V). Why?
0 Kudos
Highlighted
Xilinx Employee
Xilinx Employee
6,271 Views
Registered: ‎07-31-2012

Can you create this question as a new post please?

Thanks,
Anirudh

PS: Please MARK this as an answer in case it helped resolve your query.Give kudos in case the post guided you to a solution.
0 Kudos
Highlighted
Contributor
Contributor
6,255 Views
Registered: ‎09-04-2013

got it...sorry for that

0 Kudos