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Voyager
Voyager
661 Views
Registered: ‎02-01-2013

Just a documentation thing--or am I misapprehending the concept of 'global'?

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We have a customer who is hung-up on this line from UG472:

2019-01-14_18-48-21.jpg

The customer contends that since global clock lines only reach the half of the chip on which they entered the chip via a clock-capable pin, we need to have separate clock inputs for the top AND bottom halves.  All because of this line.

It's our assertion that global buffers reach everything in a chip, based on a fair understanding of 'global' clocks, and on this other assertion from the same UG:

2019-01-14_18-26-22.jpg

It seems to me that the notion of top-half and bottom-half BUFG's was conflated with the intent to simply say "clock-capable inputs can drive global clock lines"--for some reason, in order to lengthen this sentence into the monstrosity that it has become.

Someone please break the documentation tie.

-Joe G.

 

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591 Views
Registered: ‎01-22-2015

Re: Just a documentation thing--or am I misapprehending the concept of 'global'?

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Joe,

Be sure to read Avrum's post in the following thread.

https://forums.xilinx.com/t5/Timing-Analysis/In-User-guide-472-mentioned-that-quot-The-top-and-bottom/m-p/929578#M15886%2Fjump-to%2Ffirst-unread-message

I think it is safe to tell your customer that we must trust the Vivado tools. That is, we rarely get involved with selecting and locating BUFG – the tools do that for us. If the tools are having trouble selecting/locating the "right" BUFG then they should warn us and/or we should see the consequencing of the problem during timing analysis.

Also, your customer's proposal to have "..separate clock inputs for the top AND bottom halves" is possible but makes life difficult.  Even if these "separate clock inputs" are coming from the same external clock, once you bring them into the FPGA and thru an MMCM/BUFG then you can no longer consider them to be synchronous.

Mark

4 Replies
Highlighted
633 Views
Registered: ‎01-22-2015

Re: Just a documentation thing--or am I misapprehending the concept of 'global'?

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Hi Joe,

I agree with your interpretation of the “global scope” for BUFG.   Here’s some things that might help you convince the customer:

  1. UG472, page 15: “The top and bottom division separates two sets of global clock buffers (BUFGs) and imposes some limitations on how they can be connected. However, BUFGs do not belong to a clock region and can reach any clocking point on the device.”

  2. UG472, page 17: “The global clock buffer can drive into every region through the HROW even if not physically located there.”

  3. Create a small project with an MMCM whose clock output drives (through a BUFG) to cells in the top and bottom half of the device. Open the implemented design, select all the circuits in the design, and show the customer the Device view. There you will physically see that the BUFG is directly driving cells in both the top and bottom half of the device.  I have created small project for a Kintex-7 to demonstrate what I mean.  The images below are from this project. Note how the MMCM and BUFG (found inside the CLKGEN2 black box) drive cells in the top and bottom of the device.  Also note for the Kintex-7 that all BUFG are located in the yellow-oval at the center of the device.

Cheers,
Mark
K7_schem.jpgK7_dev.jpg

 

Tags (1)
592 Views
Registered: ‎01-22-2015

Re: Just a documentation thing--or am I misapprehending the concept of 'global'?

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Joe,

Be sure to read Avrum's post in the following thread.

https://forums.xilinx.com/t5/Timing-Analysis/In-User-guide-472-mentioned-that-quot-The-top-and-bottom/m-p/929578#M15886%2Fjump-to%2Ffirst-unread-message

I think it is safe to tell your customer that we must trust the Vivado tools. That is, we rarely get involved with selecting and locating BUFG – the tools do that for us. If the tools are having trouble selecting/locating the "right" BUFG then they should warn us and/or we should see the consequencing of the problem during timing analysis.

Also, your customer's proposal to have "..separate clock inputs for the top AND bottom halves" is possible but makes life difficult.  Even if these "separate clock inputs" are coming from the same external clock, once you bring them into the FPGA and thru an MMCM/BUFG then you can no longer consider them to be synchronous.

Mark

Voyager
Voyager
577 Views
Registered: ‎02-01-2013

Re: Just a documentation thing--or am I misapprehending the concept of 'global'?

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Thanks, Mark.  I hadn't seen that post. @avrumw did a great job of laying it all out.  Perhaps Xilinx should copy & past his reply into the next release of UG472. :-)

I hate to say it, but at times, it looks like Xilinx trimmed the staff in the ol' documentation department. Years ago, docs like UG472 were all crisp and clear, with nary an error to be found. Not anymore, though. Now, besides trying to understand technical concepts, one must occasionally struggle through poor language constructions. 

There should be a forum (or a simple board) where users--maybe not all of us, but some of us--can post documentation issues.

Thanks again.

-Joe G.

 

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556 Views
Registered: ‎01-22-2015

Re: Just a documentation thing--or am I misapprehending the concept of 'global'?

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You’re welcome, Joe.

     There should be a forum (or a simple board) where users…can post documentation issues
Good idea!  Hopefully the Forum moderators will pick up on your suggestion.

Until then, try the “Send Feedback” link at the bottom of each page in Xilinx documents. I’ve gotten some response to documentation improvement suggestions that I’ve sent this way.
send_feedback.jpg
Also, putting nice tags on threads (I put “BUFG top+bot” on yours) helps others find and solve problems caused by unclear documentation.

Mark