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shirley_yang
Observer
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Registered: ‎05-12-2016

K7 GTX reference clock problem

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Hi,

I am using one GTX transceiver ( wired to SMA connectors, GTXE2_CHANNEL_X0Y8, Bank117) on board KC705.

Now i pretend to build a loop-back design for GTX and i want to choose MGTREFCLK0 SGMII_CLK in the same quad which has 125mhz,  as the reference clock.Because i have no external clock resources.

However, i always get the failed timing error after the implementation.

I am not sure, if SGMII clock is specified for SGMII application or can i also  use this as the reference clock

if not, must i programm si5324?

 

Thanks

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ashishd
Xilinx Employee
Xilinx Employee
13,108 Views
Registered: ‎02-14-2014

Hello @shirley_yang,

 

just want to firstly confirm: i dont need to configure SGMII CLK or provide the external clk for  SGMII CLK,right? It has 125mhz itself and all i need to do is just to connect my ref clk signal with the IO pins of SGMII CLK, correct?

 

--> Yes this is correct.

 

When I checked the .xci file, it is observed that clock selection is incorrect. You have selected MGTREFCLK1 but SGMII_CLK is connected to MGTREFCLK0 on KC705 board. You need to correct this connection. Are you providing DRP clock through external oscillator on board? If this is not the case, then you can generate example design for default value of DRP clock (60 MHz) and provide it by using system clock which is 200 MHz (AD12/AD11 pins). You need to use clocking wizard / MMCM instantiation to convert 200 MHz to 60 MHz.

Regards,
Ashish
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vuppala
Xilinx Employee
Xilinx Employee
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Registered: ‎04-16-2012

Hi @shirley_yang

 

You can connect SGMII_CLK to GTXE2_CHANNEL_X0Y8 transceiver. So your implementation looks correct.

Can you share the timing errors here? Are you encountering timing errors on SGMII_CLK??

 

Thanks,

Vinay

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ashishd
Xilinx Employee
Xilinx Employee
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Registered: ‎02-14-2014

Hello @shirley_yang,

 

I believe error to be specific to your IP customization. Can you attach .xci file to investigate this further?

Regards,
Ashish
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yenigal
Xilinx Employee
Xilinx Employee
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Registered: ‎02-06-2013

Hi

 

Which version of the core are you using?

 

Check if there are any critical warning on core constraints not be applied and attach the timing paths that are failing.

Regards,

Satish

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shirley_yang
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Registered: ‎05-12-2016

HI vuppala,

thanks for your reply!

Timing Error: 

  • [Timing 38-282] The design failed to meet the timing requirements. Please see the timing summary report for details on the timing violations.
  • Check Timing -> no_output_delay -> TRACK_DATA_OUT 
  • Intra-Clock Paths -> drpclk_in_i (i've found several violations with this clk, which not SGMII_CLK  but system CLK. )
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shirley_yang
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Registered: ‎05-12-2016

hi ashishd,

 

Thanks for your reply.

I've attached.xci file.

 

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shirley_yang
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Registered: ‎05-12-2016

Hi yenigal,

 

thanks for your reply!

 

The vision of the GTX core is 7 series FPGAs Transceivers Wizyard(3.6).

 

Timing Error: 

  • [Timing 38-282] The design failed to meet the timing requirements. Please see the timing summary report for details on the timing violations.
  • Check Timing -> no_output_delay -> TRACK_DATA_OUT 
  • CLK: drpclk_in_i           WNS(ns) : -0.913     TNS(ns):-25.459          TNS Failing Endpoints: 105     TNS Total Endpoints : 4627      WHS(ns):-0.816      THS(ns): -12.326     THS Failing Endpoints: 42       THS Total Endpoints: 4627     WPWS(ns): -0.714       TPWS(ns):-0.714       TPWS Failing Endpoints:1      TPWS Total Endpoints  :  2677  

  • And i also get 2 critical warning with DRC violations.   

 NSTD-1#1 Critical Warning

Unspecified I/O Standard 

3 out of 9 logical ports use I/O standard (IOSTANDARD) value 'DEFAULT', instead of a user assigned specific value. This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all I/O standards. This design will fail to generate a bitstream unless all logical ports have a user specified I/O standard value defined. To allow bitstream creation with unspecified I/O standard values (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks NSTD-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: DRP_CLK_IN_P, DRP_CLK_IN_N, TRACK_DATA_OUT.
Related violations: <none>

 

 

UCIO-1#1 Critical Warning
Unconstrained Logical Port
1 out of 9 logical ports have no user assigned specific location constraint (LOC). This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all pin locations. This design will fail to generate a bitstream unless all logical ports have a user specified site LOC constraint defined. To allow bitstream creation with unspecified pin locations (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks UCIO-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: TRACK_DATA_OUT.
Related violations: <none>

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shirley_yang
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Registered: ‎05-12-2016

Sorry, I'm still new to GTX and just want to firstly confirm: i dont need to configure SGMII CLK or provide the external clk for  SGMII CLK,right? It has 125mhz itself and all i need to do is just to connect my ref clk signal with the IO pins of SGMII CLK, correct?

 

And  i also try to connect the ref clock pin to SMA_MGT_REFCLK_N and SMA_MGT_REFCLK_P (just connected, without actual clock signal) , which should be external provided. However , i've got  the same timing error and the same timing falling path : drpclk. I used system clk  200mhz as drpclk. but  actually it is limited to 175 mhz in the wizard. But the strange thg is that, the exsample design xapp1200 from Xilinx also uses 200mhz...  I am confused now.....

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ashishd
Xilinx Employee
Xilinx Employee
13,109 Views
Registered: ‎02-14-2014

Hello @shirley_yang,

 

just want to firstly confirm: i dont need to configure SGMII CLK or provide the external clk for  SGMII CLK,right? It has 125mhz itself and all i need to do is just to connect my ref clk signal with the IO pins of SGMII CLK, correct?

 

--> Yes this is correct.

 

When I checked the .xci file, it is observed that clock selection is incorrect. You have selected MGTREFCLK1 but SGMII_CLK is connected to MGTREFCLK0 on KC705 board. You need to correct this connection. Are you providing DRP clock through external oscillator on board? If this is not the case, then you can generate example design for default value of DRP clock (60 MHz) and provide it by using system clock which is 200 MHz (AD12/AD11 pins). You need to use clocking wizard / MMCM instantiation to convert 200 MHz to 60 MHz.

Regards,
Ashish
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shirley_yang
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Registered: ‎05-12-2016

Hi ashishd,

 

Thanks for your reply! When i added MMCM for DRP clock, the error disappeared! and the design works now!

 

Thank u so much !

 

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ashishd
Xilinx Employee
Xilinx Employee
4,962 Views
Registered: ‎02-14-2014

Hello @shirley_yang,

 

Since the issue is resolved, feel free to close the thread by marking helpful post as solution.

Regards,
Ashish
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