03-07-2014 01:28 PM
I’ll be designing a PCB with a XC7K410T. I’ve looked at all 26 pages from this forum. Regarding power sequencing, http://forums.xilinx.com/t5/7-Series-FPGAs/Need-Power-on-sequencing-information-on-Kintex7-series/td-p/268816 (toward the end of the string) supposes a case where VCCINT may become valid ~5 ms AFTER VCCO (=3.3V) and VCCAUX comes up ~10 ms AFTER VCCO. These don’t follow the suggested/preferred/required? sequence of : 1) VCCINT&VCCBRAM, 2) VCCAUX, 3) VCCAUX_IO, 4) VCCO [in order to minimize current draw & ensure tri-stating of I/O]. Another posting, http://forums.xilinx.com/t5/7-Series-FPGAs/Kintex7-series-Power-on-sequence-configuration/td-p/263988 seems to state that the sequencing is satisfied if all supplies (VCCINT, VCCBRAM, VCCAUX, VCCAUX_IO, VCCO) reach their respective Vmin levels within 1-2 ms of each other. Can VCCO=3.3V truly precede VCCINT or VCCAUX by as much as 5-10 ms ?
What is the power-on reset threshold voltage for these supplies ? (re: these supplies must reach these levels prior to configuration proceeding to Step 2 : Clear Configuration Memory). I’d assume : VCCINT = VCCBRAM = 0.97V (=97%Vnom), VCCAUX = VCCAUX_IO = 1.71V (=95%Vnom), since these are their respective minimum voltage levels. There is no specification in DS182 for a VCCO=3.3V, per se. [The Vmin of 1.14V applies to a VCCO=1.5V, correct ?] Would it be (3.3V)*(95%? ,97%?) ?
My apologies in advance if I’ve violated some posting rule. This is my first post.
03-07-2014 03:14 PM
The power on sequenceing is recommended for the lowest power on current except for the Vccaux before Vcco sequence. If Vcco is before Vccaux then you need to meet the TVCCO2VCCAUX spec in the datasheet. The thresholds in general are 90% of nominal for the POR to finish and proceed on to INIT_B assertion which then in turn signal the beginning of houskeeping.
04-06-2014 03:12 AM