09-17-2014 08:00 PM
Hello everyone:
I am using FPGA of K7 series , if I use LVDS signals in HR Bank of K7 , The VCCO of HR Bank must be setted to 2.5V .
if I set the Vcco to 3.3V , the board can work normally?
TKS!!
09-18-2014 06:48 AM
Hi,
Inputs can be driven by a different VCCO, only when you are not enabling the internal DIFF_TERM.
It is acceptable to have LVDS inputs in HP I/O banks even if the VCCO level is not 1.8V. LVDS outputs (and therefore bidirectional LVDS) can only be used in a bank powered at 1.8V.
Similarly, it is acceptable to have LVDS_25 inputs in HR I/O banks even if the VCCO level is not 2.5V. LVDS_25 outputs (and therefore bidirectional LVDS_25) can only be used in a bank powered at 2.5V.
However, the following must be true:
09-17-2014 08:39 PM
Hi,
Youre question is already discussed, please check below link and follow the suggetions
Regards,
Vanitha
09-18-2014 04:56 AM
Hi,
You can refer to the table 1-55 of the UG471, Table 1-55: VCCO and VREF Requirements for Each Supported I/O Standard
if the LVDS_25 is input without DIFF_TERM=TRUE the VCCO can be 3.3V, otherwise the VCCO must be 2.5V.
09-18-2014 06:48 AM
Hi,
Inputs can be driven by a different VCCO, only when you are not enabling the internal DIFF_TERM.
It is acceptable to have LVDS inputs in HP I/O banks even if the VCCO level is not 1.8V. LVDS outputs (and therefore bidirectional LVDS) can only be used in a bank powered at 1.8V.
Similarly, it is acceptable to have LVDS_25 inputs in HR I/O banks even if the VCCO level is not 2.5V. LVDS_25 outputs (and therefore bidirectional LVDS_25) can only be used in a bank powered at 2.5V.
However, the following must be true:
09-18-2014 07:06 AM
If you use LVDS-25 output then we recommend to connect VCCO = 2.5V.
In case if LVDS-25 is input, then you can use VCCO = 3.3V banks . No problem.
09-18-2014 08:23 PM
09-25-2014 05:43 AM
09-25-2014 08:59 AM
The HR bank uses the LVDS_25 IOSTANDARD not the LVDS IOSTANDARD.
09-25-2014 11:57 AM