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10,693 Views
Registered: ‎03-31-2014

K7 problem of HR BANK LVDS signals selected

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Hello everyone:

      I am using FPGA of K7 series , if I use LVDS signals in HR Bank of K7 , The VCCO of HR Bank must be setted  to 2.5V  .

if I set the Vcco to 3.3V , the board can work normally?

 

TKS!!

 

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Xilinx Employee
Xilinx Employee
16,450 Views
Registered: ‎07-31-2012

Re: K7 problem of HR BANK LVDS signals selected

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Hi,

 

Inputs can be driven by a different VCCO, only when you are not enabling the internal DIFF_TERM.

 

It is acceptable to have LVDS inputs in HP I/O banks even if the VCCO level is not 1.8V.  LVDS outputs (and therefore bidirectional LVDS) can only be used in a bank powered at 1.8V.
Similarly, it is acceptable to have LVDS_25 inputs in HR I/O banks even if the VCCO level is not 2.5V.  LVDS_25 outputs (and therefore bidirectional LVDS_25) can only be used in a bank powered at 2.5V.

However, the following must be true:

 

  1. The DIFF_TERM attribute must be FALSE - meaning, you will need to use an external differential termination resistor.
  2. Ensure that the VOD and VOCM levels of the driving device fall within the range of VIDIFF and VICM of the 7 series receiver, and that the VIN in Table 1 and 2 of the data sheet are not violated.

 

Thanks,
Anirudh

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Xilinx Employee
Xilinx Employee
10,687 Views
Registered: ‎07-11-2011

Re: K7 problem of HR BANK LVDS signals selected

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Hi,

 

Youre question is already discussed, please check below link and follow the suggetions

http://forums.xilinx.com/t5/7-Series-FPGAs/Artix-7-LVDS-Clock-Input-HR-Bank-with-VCCO-1-8V/td-p/435592

 

Regards,

Vanitha

 

 

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Visitor xingxin
Visitor
10,672 Views
Registered: ‎06-19-2013

Re: K7 problem of HR BANK LVDS signals selected

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Hi,

You can refer to the table 1-55 of the UG471, Table 1-55: VCCO and VREF Requirements for Each Supported I/O Standard

if the LVDS_25 is input without DIFF_TERM=TRUE the VCCO can be 3.3V, otherwise the VCCO must be 2.5V.

Ben
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Xilinx Employee
Xilinx Employee
16,451 Views
Registered: ‎07-31-2012

Re: K7 problem of HR BANK LVDS signals selected

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Hi,

 

Inputs can be driven by a different VCCO, only when you are not enabling the internal DIFF_TERM.

 

It is acceptable to have LVDS inputs in HP I/O banks even if the VCCO level is not 1.8V.  LVDS outputs (and therefore bidirectional LVDS) can only be used in a bank powered at 1.8V.
Similarly, it is acceptable to have LVDS_25 inputs in HR I/O banks even if the VCCO level is not 2.5V.  LVDS_25 outputs (and therefore bidirectional LVDS_25) can only be used in a bank powered at 2.5V.

However, the following must be true:

 

  1. The DIFF_TERM attribute must be FALSE - meaning, you will need to use an external differential termination resistor.
  2. Ensure that the VOD and VOCM levels of the driving device fall within the range of VIDIFF and VICM of the 7 series receiver, and that the VIN in Table 1 and 2 of the data sheet are not violated.

 

Thanks,
Anirudh

PS: Please MARK this as an answer in case it helped resolve your query.Give kudos in case the post guided you to a solution.

View solution in original post

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Xilinx Employee
Xilinx Employee
10,658 Views
Registered: ‎08-01-2012

Re: K7 problem of HR BANK LVDS signals selected

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If you use LVDS-25 output then we recommend to connect VCCO = 2.5V.

 

In case if LVDS-25 is input, then you can use VCCO = 3.3V banks . No problem. 

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10,639 Views
Registered: ‎03-31-2014

Re: K7 problem of HR BANK LVDS signals selected

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TKS for your answer!
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Adventurer
Adventurer
10,557 Views
Registered: ‎11-18-2013

Re: K7 problem of HR BANK LVDS signals selected

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Hello,
We are using a Xilinx 35T device, with Bank14 (powered at 2.5V) having a LVDS input clock.
The same constraints were made in the xdc file. However implementation throws the following error:
[Drc 23-20] Rule violation (BIVB-1) Bank IO standard Support - Bank 14 has incompatible IO(s) because: The LVDS I/O standard is not supported. Move the following ports or change their properties:
CLK_IN_PLL

In my understanding all banks support LVDS I/O standard. Please advise.
Thanks,
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Xilinx Employee
Xilinx Employee
10,553 Views
Registered: ‎01-03-2008

Re: K7 problem of HR BANK LVDS signals selected

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The HR bank uses the LVDS_25 IOSTANDARD not the LVDS IOSTANDARD.

------Have you tried typing your question into Google? If not you should before posting.
Too many results? Try adding site:www.xilinx.com
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Adventurer
Adventurer
10,547 Views
Registered: ‎11-18-2013

Re: K7 problem of HR BANK LVDS signals selected

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Thanks mcgett!
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