UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
2,131 Views
Registered: ‎04-04-2017

KC705 Aurora 8B10B INIT_clk

Jump to solution

Hello!

 

I'm trying to use Aurora 8b/10b on KC705 and I'm confused about the INIT_clk. In table Table 2-12: Status and Control Ports from PG046 Aurora 8B/10B v11.1 he says:

 

" The init_clk_in port is required because user_clk stops when gt_reset is asserted. It is recommended that the frequency chosen for init_clk_in be lower than the GT Reference Clock input frequency. "

 

If I use an 125.000 MHz (MGTREFCLK0 - SGMII clock) as GT Refclk I'm limited to using an INIT clk [50.0 - 125.000]. The INIT clk is a Free Running Clock, but I don't have a dedicated free running board clock with 50 MHz or 125 MHz to use as input in Aurora's Core.

 

In XAPP1211 (v1.0) Page 11 he says:

 

" 9. Change the comment from 50 MHz to 200 MHz "

 

Here he changes manually the constraints to use 200 MHz free running board clock, but the recommendation is to use a lower frequency than GT Refclk. 

 

What should I expect if I do that? Who's right? 

 

 

Thanks for the suggestions!

0 Kudos
1 Solution

Accepted Solutions
3,519 Views
Registered: ‎04-04-2017

Re: KC705 Aurora 8B10B INIT_clk

Jump to solution

I followed the suggested recommendation on page 32 of KC705 Evaluation Board. 7.UG810 (v1.7) July 8, 2016

Then I used the following block found in the .ZIP of the KC705 Si5324 Design (October 2014)

 

Clock_Forwarding_Output_Pins.png

 

Now I have as GTREF the 200 MHz freer unning board clock with the jitter attenuation offers by Si5324. Now I haven't the "Timing Failure" for Tx when I synthesize !!

View solution in original post

0 Kudos
3 Replies
2,079 Views
Registered: ‎04-04-2017

Re: KC705 Aurora 8B10B INIT_clk

Jump to solution

In resume:


I've been testing and if we change the clock manually in XDC to 200 MHz instead of 50 MHz the timing will be fail for TX Mode but not for RX Mode. So, I think it's because that we have that recommendation in the Product Guide (timing failure). 

 

More suggestions? I will leave the Post in open to more discussions.

0 Kudos
3,520 Views
Registered: ‎04-04-2017

Re: KC705 Aurora 8B10B INIT_clk

Jump to solution

I followed the suggested recommendation on page 32 of KC705 Evaluation Board. 7.UG810 (v1.7) July 8, 2016

Then I used the following block found in the .ZIP of the KC705 Si5324 Design (October 2014)

 

Clock_Forwarding_Output_Pins.png

 

Now I have as GTREF the 200 MHz freer unning board clock with the jitter attenuation offers by Si5324. Now I haven't the "Timing Failure" for Tx when I synthesize !!

View solution in original post

0 Kudos
Observer amit_kumar
Observer
255 Views
Registered: ‎06-19-2019

Re: KC705 Aurora 8B10B INIT_clk

Jump to solution

can you explain the block little bit? How is it solving the above problem because I am using kintex ultrascale evaluation board which has 250 MHz of free running clock. I have LVDS programmable clock on the board. I used that to supply INIT_CLK with a frequency of 156.25 MHZ but I got a critical warning saying 

[Vivado 12-1411] Cannot set LOC property of ports, Could not find a valid bel for the shape with the following elements:
INIT_CLK_P
init_clk_ibufg_i/IBUFCTRL_INST
INIT_CLK_N
init_clk_ibufg_i/DIFFINBUF_INST
["D:/amit/example_sameclk/aurora_8b10b_0_ex/imports/aurora_8b10b_0_exdes.xdc":75]

during implementation.

I need help.
Thanks

 

0 Kudos