‎09-04-2019 12:04 AM
I am working on the kintex-7 5-input Dynamically Reconfiguration lut(CFGLUTs). Do you know the timing diagram of LUT reconfiguration,or To reconfigure the data serial input (CDI),how to set the CE pin,how many clks should CE last
‎09-07-2019 05:03 AM - edited ‎09-07-2019 12:18 PM
-building a Trojan virus are we? 😊
I understand from <here> that the CFGLUT5 is built from a SLICEM of Kintex-7 as a SRL32. The timing diagram for SLR32 (and thus CFGLUT5) is shown in Fig 5-7 of UG474(v1.8).
When clocking INIT value into CFGLUT5, my simulation in Vivado v2018.3 shows that CE of CFGLUT5 should be raised before rising-edge-1 of CLK and lowered before rising-edge-33 of CLK (similar to WE in Fig 5-7 of UG474). Page 293 of UG953 (v2019.1) gives INIT=x"FFFF8000" example that you can use for testing.
Mark
‎09-07-2019 05:03 AM - edited ‎09-07-2019 12:18 PM
-building a Trojan virus are we? 😊
I understand from <here> that the CFGLUT5 is built from a SLICEM of Kintex-7 as a SRL32. The timing diagram for SLR32 (and thus CFGLUT5) is shown in Fig 5-7 of UG474(v1.8).
When clocking INIT value into CFGLUT5, my simulation in Vivado v2018.3 shows that CE of CFGLUT5 should be raised before rising-edge-1 of CLK and lowered before rising-edge-33 of CLK (similar to WE in Fig 5-7 of UG474). Page 293 of UG953 (v2019.1) gives INIT=x"FFFF8000" example that you can use for testing.
Mark
‎09-10-2019 07:40 PM
Thanks so much. According to your reply,I have solved my problem!