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215 Views
Registered: ‎02-26-2019

Kintex-7 CFGLUTs(reconfigurable LUTs) timing diagram

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I am working on the kintex-7 5-input Dynamically Reconfiguration lut(CFGLUTs). Do you know the timing diagram of LUT reconfiguration,or To reconfigure the data serial input (CDI),how to set the CE pin,how many clks should CE last

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155 Views
Registered: ‎01-22-2015

Re: Kintex-7 CFGLUTs(reconfigurable LUTs) timing diagram

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@lilia20190227 

-building a Trojan virus are we?  😊

I understand from <here> that the CFGLUT5 is built from a SLICEM of Kintex-7 as a SRL32.  The timing diagram for SLR32 (and thus CFGLUT5) is shown in Fig 5-7 of UG474(v1.8).   

When clocking INIT value into CFGLUT5, my simulation in Vivado v2018.3 shows that CE of CFGLUT5 should be raised before rising-edge-1 of CLK and lowered before rising-edge-33 of CLK (similar to WE in Fig 5-7 of UG474).  Page 293 of UG953 (v2019.1) gives INIT=x"FFFF8000" example that you can use for testing.

Mark

 

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156 Views
Registered: ‎01-22-2015

Re: Kintex-7 CFGLUTs(reconfigurable LUTs) timing diagram

Jump to solution

@lilia20190227 

-building a Trojan virus are we?  😊

I understand from <here> that the CFGLUT5 is built from a SLICEM of Kintex-7 as a SRL32.  The timing diagram for SLR32 (and thus CFGLUT5) is shown in Fig 5-7 of UG474(v1.8).   

When clocking INIT value into CFGLUT5, my simulation in Vivado v2018.3 shows that CE of CFGLUT5 should be raised before rising-edge-1 of CLK and lowered before rising-edge-33 of CLK (similar to WE in Fig 5-7 of UG474).  Page 293 of UG953 (v2019.1) gives INIT=x"FFFF8000" example that you can use for testing.

Mark

 

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108 Views
Registered: ‎02-26-2019

Re: Kintex-7 CFGLUTs(reconfigurable LUTs) timing diagram

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Thanks so much. According to your reply,I have solved my problem!

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