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Visitor
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Registered: ‎12-05-2018

Kintex-7 Power-on Sequencing

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We are aware of the Xilinx power-on sequencing recommendations in the datasheet, and we designed a series of voltage regulators to turn power on in the recommended order.

We have discovered after the fact that we used a voltage regulator with a power good pin that doesn’t function when the regulator is powered but not enabled (i.e. the regulator has a shutdown pin, and when that shutdown pin is driven low, the power good pin acts as if that regulator has good output power).  This is not captured in the regulator datasheet, but the manufacturer confirmed today that this is the behavior of the power good pin. 

This regulator, used for the MGT 1.8V, is the last regulator in the chain.  Unfortunately, we rely on this power good pin to prevent the FPGA from configuring if a voltage regulator earlier in the chain fails to power up. 

Our concern is if one of the earlier regulators, say the 1V core power, fails to come up, and now our FPGA tries to configure without all the rails powered, is there risk the FPGA I/O may not come up tristated (which is what we believe is the underlying reason there could be excessive current draw if the FPGA power-on sequencing is not respected)?  Are there any combinations of power rail failures that might increase that risk?  For example, if the 1V core fails but all other rails come up, is the risk just as high as if we have a VCCO or VCCAUX rail fail to come up?

Any guidance would be greatly appreciated.

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Registered: ‎07-23-2015

@rkriner  You got that right. For the IO's, while powering ON, it depends on your PUDC_B pin setup as well. If is is HIGH, then since you are following the sequence, they will be in tristate. If you have failures in one your power supplies, IO's may or may not be in tristate depending on the power sequence happening as we haven't tested any other sequence other than the one in datasheet.  

As long as you are not driving anything into the FPGA while powering up, you are Ok irrespective of the state of the IO. 

- Giri
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Registered: ‎09-17-2018

Understand the recommended sequense is gauranteed,

Specified in the data sheet.  Other sequences work just fine.  The current differences are minimal, and of course, do not affect reliability at all.  Tristate while powering ON is pretty silly, as powering ON eans IO is at 0v for awhile, even though it is not being pulled high or low, it isn't really tristate as the protection diodes pull the IO pin to within a diode drop of ground (effectively all IO are ground until Vcco gets to a few volts).

I suspect everything will work just fine with your sequence.

If you desire Xilinx to guarantee your board, they ONLY do that for the stated sequence, exactly.  But, they only guarantee the data sheet power on current values (not to excede) - nothing else.

You could get them to guarantee your setup, but I suspect you might have to be a Cisco or Huawei to get that kind of treatment ...

l.e.o.

 

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Registered: ‎07-23-2015

@rkriner  For configuration, 7 series devices require power on the VCCO_0, VCCAUX, VCCBRAM, and VCCINT pins. If not the POR circuit will not trigger and configuration will not start. So if one of your rails among the above doesn't power up, the device will not begin configuration. So you are good.

As @lowearthorbit  mentioned, powering any sequence is fine provided you are fine with the caveat of IO's "may not" be in tristate and there "may be" higher current draw. No reliability concerns though. 

If you have VCCO of 3.3V in a HR Bank, you need to be aware of the TVCCO2VCCAUX specification as well and need to adhere to it. Check "Power-On/Off Power Supply Sequencing" section from DS182 for more details on this

 

- Giri
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There's no such thing as a stupid question. Feel free to ask but do a quick search to make sure it ain't already answered.
Keep conversing, give Kudos and Accept Solution when you get one.
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Registered: ‎12-05-2018

Giri,

Thanks for the prompt response.

We are not using 3.3V for any FPGA power rails; our highest VCCO is 2.5V. (But thank you for mentioning TVCCO2VCCAUX.)

Our power sequencing is: VCCINT/VCCBRAM (single regulator) => VCCAUX (1.8V) and MGTAVCC (both regulators enabled concurrently) => VCCO (2.5V) and MGTAVTT and MGTAVCCAUX (all 3 regulators enabled concurrently). If any regulator fails to come up, all the regulators after the next set of “=>” symbols won’t be enabled.

Hence if VCCINT/VCCBRAM doesn’t power up, none of the remaining rails will be enabled. If VCCAUX (1.8V) or MGTAVCC don’t power up, we don’t enable VCCO (2.5V), MGTAVTT, or MGTAVCCAUX. And finally, as mentioned in the initial inquiry, the FPGA configuration would normally be held off until the MGTAVCCAUX regulator reported power good. We now know its power good pin doesn’t function unless it’s enabled, so if one of the upstream regulators failed, the FPGA could be commanded to configure without all the power rails on (and this is what drove the initial inquiry).

For completeness we should mention there is a supervisory POR device after the MGTAVCCAUX regulator power good pin. That supervisory POR device has a time constant more than long enough for all the power rails to come up under normal circumstances. An output from that supervisory POR device is what drives the FPGA’s PROGRAM_B pin, and a buffered copy holds off the INIT_B pin. (This general approach is one we’ve used on many 7-Series designs and it has worked well.)  

That all said, let me repeat back what I think the takeaway is.

If any of the key voltage rails (VCCO_0, VCCAUX, VCCBRAM, and VCCINT) don't power up, the POR circuit inside the Kintex-7 will prevent the FPGA from trying to configure regardless of what the user does at the PROGRAM_B or INIT_B pins. In other words, the FPGA user I/O would remain tristated (or put another way, the FPGA user I/O pins cannot enter a low impedance state where they could drive any appreciable current in either direction). 

Please confirm, and thanks again.

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Registered: ‎07-23-2015

@rkriner  You got that right. For the IO's, while powering ON, it depends on your PUDC_B pin setup as well. If is is HIGH, then since you are following the sequence, they will be in tristate. If you have failures in one your power supplies, IO's may or may not be in tristate depending on the power sequence happening as we haven't tested any other sequence other than the one in datasheet.  

As long as you are not driving anything into the FPGA while powering up, you are Ok irrespective of the state of the IO. 

- Giri
--------------------------------------------------------------------------------------------------------------------
There's no such thing as a stupid question. Feel free to ask but do a quick search to make sure it ain't already answered.
Keep conversing, give Kudos and Accept Solution when you get one.
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Registered: ‎12-05-2018
That covers it. Thanks again Giri.
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