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subhashkrishnan
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Registered: ‎06-28-2018

Kintex 7 XC7K325T - DRC error

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Reference: custom RTL module on Genesys 2 board (XCK325T)

 

I have defined constraints in the xdc file for external differential clock input namely CLK_FPGA_SYNTH_N , and CLK_FPGA_SYNTH_P, which is connected via MRCC pins (D13 and D12) in bank-18. This bank is connected with VCCO=1.8V and all other lines in this bank are set with IOSTANDARD  LVCMOS18.

 

The definition for CLK_FPGA_SYNTH_N and CLK_FPGA_SYNTH_P in xdc file is as follows:

set_property -dict { PACKAGE_PIN D13   IOSTANDARD LVDS } [get_ports { CLK_FPGA_SYNTH_N }];

set_property -dict { PACKAGE_PIN D12   IOSTANDARD LVDS } [get_ports { CLK_FPGA_SYNTH_P }];

 

However  DRC error is detected during 'place design':

[DRC BIVB-1] Bank IO standard Support: Bank 18 has incompatible IO(s) because: The LVDS I/O standard is not supported.  Move the following ports or change their properties:

CLK_FPGA_SYNTH_P

 

How to resolve this error?

 

Thanks and

Best Regards

--Subhash

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tenzinc
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949 Views
Registered: ‎09-18-2014

Subhashkrishnan,

 

Well you see LVDS is available for only HP banks and you are using bank 18 which is an HR bank. So you should use LVDS_25. Just make sure that DIFF_TERM isn't used for termination. Either external differential termination should be used or you should just use DIFF_SSTL/HSTL variant with IN_TERM if you HAVE to use internal termination. 

 

 

Regards,

T

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tenzinc
Moderator
Moderator
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Registered: ‎09-18-2014

Subhashkrishnan,

 

Well you see LVDS is available for only HP banks and you are using bank 18 which is an HR bank. So you should use LVDS_25. Just make sure that DIFF_TERM isn't used for termination. Either external differential termination should be used or you should just use DIFF_SSTL/HSTL variant with IN_TERM if you HAVE to use internal termination. 

 

 

Regards,

T

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subhashkrishnan
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Registered: ‎06-28-2018

Thank you. I had corrected this till bank-17, but somehow overlooked. 

Thanks for support

 

Best Regards

--Subhash

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