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mo69_hoseini
Adventurer
Adventurer
2,680 Views
Registered: ‎11-23-2017

Kintex-7 decoupling capacitors

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Hi,

I'm designing a board based on a XC7K325T-2FFG FPGA. In addition to the user guides of 7 Series, my other reference is the schematic of KC705.

According to UG476, one 4.7uF capacitor is needed per group of MGT power pins.

cap1.JPG

 

My first question is that what does "per group" mean? Does it mean that I should consider only one capacitor for MGTAVCC, one capacitor for MGTAVTT and another capacitor for MGTVCCAUX? or I should insert one capacitor per power pins of each MGT bank?

On the other hand, KC705 schematic uses considerably more capacitors with various values (below image).

cap2.jpg

So what should I do? Should I use various and many capacitors like KC705? or the 4.7uF is enough?

This is my long-standing question: If I use many capacitors, may I encounter negative impacts?

It should be noted that my board is going to have 16 SFP+ ports.

 

Thanks in advance.

 

 

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umamahe
Xilinx Employee
Xilinx Employee
3,111 Views
Registered: ‎08-01-2012

@mo69_hoseini--Below are my comments for your queries

 

Q1) --My first question is that what does "per group" mean? Does it mean that I should consider only one capacitor for MGTAVCC, one capacitor for MGTAVTT and another capacitor for MGTVCCAUX? or I should insert one capacitor per power pins of each MGT bank?

 

 

Q2) --So what should I do? Should I use various and many capacitors like KC705? or the 4.7uF is enough? This is my long-standing question: If I use many capacitors, may I encounter negative impacts?It should be noted that my board is going to have 16 SFP+ ports.

 

  • At the time of KC705 board design the Kintex-7 characterization might not completed 100%. So third party board designer may not follow user guide recommendations.
  • Eval Boards are designed well in advance to Chip arrival and so most of them will tend to be Over designed or not following the Decoupling Caps requirement in PCB Design guide. The Decoupling requirements mentioned in PCB Design guide/MGT user guides are based on characterisation results and so is the recommendation that needs to be followed.

 

 

FYI: Xilinx recommends decoupling capacitors in PCB design user guides based on wide characterization which covers supported operating frequency ranges and load requirements of that particular FPGA supply rail. So following user guide recommendations recommended and safe. 

To understand the decoupling capacitor theory you may refer http://www.xilinx.com/support/documentation/application_notes/xapp623.pdf . Also presented in respective device family PCB design user guide.

 

________________________________________________

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3 Replies
embedded
Advisor
Advisor
2,641 Views
Registered: ‎06-09-2011

@mo69_hoseini,

First of all, mentioned user guide explains the minimum required capacitors needed for device to work in the specified conditions. If you have enough space according to the package and your PCB space you are better use a range of capacitors - even more than what is suggested in the user guide. Besides, there are different packages which have numerous GTX banks in every device. For example, the mentioned device - XC7K325T - with Fxx900 packages there are upto 4 GTX banks. So, you need to use specified capacitors for each bank independently.

 

 

Hope this will help,

Hossein

Thanks,
Hossein
umamahe
Xilinx Employee
Xilinx Employee
3,112 Views
Registered: ‎08-01-2012

@mo69_hoseini--Below are my comments for your queries

 

Q1) --My first question is that what does "per group" mean? Does it mean that I should consider only one capacitor for MGTAVCC, one capacitor for MGTAVTT and another capacitor for MGTVCCAUX? or I should insert one capacitor per power pins of each MGT bank?

 

 

Q2) --So what should I do? Should I use various and many capacitors like KC705? or the 4.7uF is enough? This is my long-standing question: If I use many capacitors, may I encounter negative impacts?It should be noted that my board is going to have 16 SFP+ ports.

 

  • At the time of KC705 board design the Kintex-7 characterization might not completed 100%. So third party board designer may not follow user guide recommendations.
  • Eval Boards are designed well in advance to Chip arrival and so most of them will tend to be Over designed or not following the Decoupling Caps requirement in PCB Design guide. The Decoupling requirements mentioned in PCB Design guide/MGT user guides are based on characterisation results and so is the recommendation that needs to be followed.

 

 

FYI: Xilinx recommends decoupling capacitors in PCB design user guides based on wide characterization which covers supported operating frequency ranges and load requirements of that particular FPGA supply rail. So following user guide recommendations recommended and safe. 

To understand the decoupling capacitor theory you may refer http://www.xilinx.com/support/documentation/application_notes/xapp623.pdf . Also presented in respective device family PCB design user guide.

 

________________________________________________

Please mark this post as an "Accept as solution" in case if it helped to resolve your query. So that it will help to other forum users to directly refer to the answer.

Give kudos to this post in case if you think the information is useful and reply oriented.

View solution in original post

umamahe
Xilinx Employee
Xilinx Employee
2,551 Views
Registered: ‎08-01-2012

@mo69_hoseini-

Did your query answered? If yes, please close the thread by clicking on “Accept as Solution” tab for that particular reply posts which were more helpful for you. That will be helpful for other users.

________________________________________________

Please mark this post as an "Accept as solution" in case if it helped to resolve your query. So that it will help to other forum users to directly refer to the answer.

Give kudos to this post in case if you think the information is useful and reply oriented.

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