01-12-2020 01:13 PM
After turning on the custom board, Kintex FPGA destroyed - power ralils pass to short cirquit.
This is the second case, the second board.
Resistance of VCCINT, VCCAUX and VCCIO - 0.5 Om.
Power consumption this FPGA, before destroyed - 0.5W.
Now I can’t say exactly how consistent the power up sequence. According to the scheme - VCCO 1.5 volt, turns before on 7-10 ms, than VCCINT 1V, and VCCAUX 1.8V.
After that, power suplies of VCCO 2.5, VCCAUX and VCCO 1.8 also distroed - short cirquit between input voltage and output voltage.
Thus, it is not entirely clear what caused this situation.
My question is, is it possible that something is wrong power up sequence for a little time ~ 10 ms will cause destruction of FPGA with consumption 0.5W.
01-14-2020 10:09 AM
I will addition information. I use XC7K160T-2FBG676I, acquired in Digi-Key.
1. Each of these two boards worked for at least two weeks.
2. I checked the voltages
VCCINT, VCCBRAM - 0.99V
VCCAUX, VCCAUX_IO - 1.79 V
VCCO for banks 12, 34, 33, 32 - 1.54 V
VCC0 for banks 13, 14, and bank 0 - 1.79
VCC0 for bank 15, 16. - 2.5 v
VCCADC - connected to VCCAUX.
VP, VN VREFP, VREFN, GNDADC, VCCBAT - tied to ground.
PUDC_B - 470 Om to ground.
DXP DXN - to ground.
3. CFGBVS tied to ground. I use master SPI for configuration.
From Table 2-6, when i use 1.8 V configuration interface i should use same voltage 1.8 V for banks 0 and bank 14.
Bank 15 can be any voltage, only if in configuration time configuration pins not used.
Caution! When CFGBVS is set to Low for 1.8V/1.5V I/O operation, the VCCO_0 and I/O signals
to bank 0 must be 1.8V (or lower). VCCO_14 and VCCO_15 must also be 1.8V/1.5V if
configuration I/O in those banks are used during configuration.
In my board i not use configuration pins in bank 15
In this case i can use 2.5 volts for supply bank 15?
3 Power up sequence.
I find, that i turned on power of VCCAUX, VCCAUX_IO, VCC0_13, 14, VCC_0 (1.8V) on 2.5 ms earlier than VCCINT.
can this cause the destruction of the chip?
01-18-2020 06:46 AM
I still have not found the cause of the failure of the two FPGA.
I would like to receive a response from Xilinx specialists.
01-18-2020 08:51 AM
1) The schematic you have shown for bank 15 says XC7K325T but your text says XC7K160T. Which FPGA are you using?
2) On our FPGA boards, we use LDO regulators to derive the FPGA voltages needed from a common +5V supply. Once, our boards were failing similar to the way you describe. We traced the problem to failing LDO regulators and not a failing FPGA – because at power-up our +5V was sending damaging voltage spikes to the LDO regulators. So, check whether it is the FPGA that has shorted power rails or it is the LDO regulators that have shorted outputs.
3) Verify that PUDC_B pulldown resistor (you say 470 ohm) is actually 470 ohm and not something larger than 1K ohm (see Table 2-4 in UG470).
4) Check devices connected to the FPGA. If they are powering up well before the FPGA then ensure they are not sending damaging current to the FPGA via an I/O pin on the FPGA (see IIN specification in Table 2 of DS182).
5) Ensure that you are specifying IO standards that are appropriate for the VCCO in each IO bank (see VCCO discussion on pg18 of UG471(v1.10)).
6) Check that you have a good ground connection between your FPGA board and other boards/devices that connect to your FPGA board.
7) If you are using a heatsink on the FPGA, then look at Tables B-1 and B-2 of UG475 for possible causes of damage.
01-18-2020 09:21 AM
This must be very frustrating,
Im not Xilinx , and have no financial connectoin to them, Im just old..
My first thoughts would be
a) Bad batch of chips ( counter fit ) as you got through a good dist, then this is all but zero ,
b) Chips miss placed on board,back to front is a clasic,,, Double sheck by eye.
c) Layout wrong, foot print back to front / inverted is a clasic, Do you have versions of these boards that do work.
d) PCB made wrong, Ive had boards made with layers missing / extra ones added , wrong order so vias short.
Get probing your spare PCB you had made that was not populated ,, !!!!
e) You have the wrong chip , get the magnifynig glass out.
f) Your applying voltage out side limits to the IO from outside the FPGA before its powered up and configured.
g) You PSU circuit is wrong, giving wrong volatges..
Only after I'd checked all that , would I start looking deeper .
As an aside, And I will be shouted at for this,
I'd say out of the last 50 designs I have been involved with at clients, only 10 % have "proper" power sequencing, .... I know, its against all the rules, and they are not boards I have designed, I get involved in other bits, but they all work, and have some have done for many years,,,,,,
01-18-2020 09:44 AM
So, I was in ICDES for 12 years, I re-designed the power ON for V5. Last I checked (Feb 2018 before I left the big X, it was still my circuit in all devices.
First, the only way to blow up a device is to greatly exceed Table I abs max specs in data sheet. Sequence WILL NOT DESTROY A PART, only blasting larger voltages (currents) will do that.
So, I would take off the blown part, replae it with load resistors, and look at the voltages for start up issues. If you do not see any, then move on to a working part and board, and repoeat.
If you never see anything exceeding the Abs Max, then I would look at ESD damage in handling. Assembly, test, packaging are all areas where improper handling, or a poorly protected device is vulnerable. A good powerful ESD zap will kill a device everytime. The damage may not actually show up right away. It might take a month before the zapped device goes to a short. Winter is ESD season with low humidity...
For example, in a system, the connector to the IO on a bank was unprotected, and no ESD protection meant those IO got zapped by handling in unpacking the system, and that IO bank would short out after awhile. This led to a re-design where ESD protection was added, and tested to verify it was doing its job.
01-19-2020 03:28 AM
In my case, along with the FPGA is damaged, the same DC-DC buck converter LTC3636-1. From its outputs fed to the FPGA 1.8 and 2.5 volts. Input voltage for this DC-DC is 10 volt.
All this happens when the laboratory power supply is turned on, from which 10 volts are taken.
In both boards, it's the same DC-DC, although in the board i use six of the same DC-DC LTC3636-1.
In this DC-DC input resistance between the input and output voltages becomes 0.6 ohm, the resistance between both output voltages and ground is 0.5 ohms, and resistance between the input voltage and ground is 0.6 ohms.
When i remove LTC3636-1, resistence betwen input voltage+10V and ground became normal, but FPGA destroyed.
If this problem were related to voltage spikes in the laboratory power supply, problems would be with others five LTC3636-1.
In a a few of days, I will have refurbished boards.
I will replace the laboratory power supply, and change power-on sequence according to the ds182.
01-19-2020 04:37 AM