We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

Showing results for 
Search instead for 
Did you mean: 
Visitor jojocp
Registered: ‎12-29-2014

Kintex power DOWN sequence



i'm currently designing the power supplies for a new Project featuring a Kintex 7 device. (XC7K70 - if it matters)
Since the power up sequencing has a great documentation and is discussed all over the internet, its implementation is pretty straight forward.

But it seems like there is not much attention paid to the power DOWN sequencing.

Even if the supplies are shut down in the correct order (reversed power up order), some rails may stay up for a decent amount of time due to the power network's capacity.

Here is an concrete example where this might cause problems:


"The voltage difference between VCCO and VCCAUX must not exceed 2.625V for longer than TVCCO2VCCAUX for each power-on/off cycle to maintain device reliability levels."

(Source: Kintex-7 Datasheet DS182)

In my System some IO Banks are powered from 3.3V and VccAux is powered from 1.8V.

While the 1.8V rail is already discharged, the 3.3V rail might still remain at its nominal voltage level due to light load conditions.
In this case the differential voltage would exceed 2.625V.


I wonder why the Kintex reference designs (and many others) do not take this into account.

Have you got experiences regarding power down sequencing?


Best regards, Jost



0 Kudos
2 Replies
Xilinx Employee
Xilinx Employee
Registered: ‎08-01-2012

Re: Kintex power DOWN sequence

@jojocp mentioned –


1) TVCCO2VCCAUX (Table 8 in data sheet) specification given with respect to TJ. (As per data sheet if TJ 125 degree C then TVCCO2VCCAUX is 300 mS. If J 85 degree C then TVCCO2VCCAUX is 800 mS). For lower junction temperature TVCCO2VCCAUX is even more time than 800 mS.


2) You mentioned that “Some rails may stay up for a decent amount of time due to the power network's capacity." Generally those capacitive charging voltages have very little potential energy. Also the junction temperature is obviously go down during power down time.


So my comment is that if you powered off all your power supply rails simultaneously then the short time retaining voltages due to power network's capacity do not affect the device reliability levels.

(Hope you will use with Xilinx PCB design user guide recommended decoupling capacitors in your board. Please wait for other contributors opinions before coming to some conclusions)


Please mark this post as an "Accept as solution" in case if it helped to resolve your query. So that it will help to other forum users to directly refer to the answer.

Give kudos to this post in case if you think the information is useful and reply oriented.

0 Kudos
Observer woko
Registered: ‎09-13-2012

Re: Kintex power DOWN sequence


But it seems like there is not much attention paid to the power DOWN sequencing.

Hi @jojocp,

we're facing a very similar situation right now. We wonder what your conclusions to this issue have been? Since your post was written 2 years ago, you definitely found a solution in the meanwhile. Would you share it to us, please?


Thanks & regards,

0 Kudos