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Visitor
Visitor
14,358 Views
Registered: ‎09-14-2011

LVDS 1.8 interface in Artix 7

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Dear Sir,

 

I have connected ADC 1.8V LVDS output to ARTIX7 FPGA but ARTIX7 has only HR banks.

So whether can i operate ARTIX7 with 1.8V LVDS input.

 

 

Regards

Amit Kumar

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Xilinx Employee
Xilinx Employee
17,699 Views
Registered: ‎07-11-2011

Hi,

 

It is true that LVDS 1.8 is in HP banks and LVDS_25 is in HR banks but if you see Table 1-55, N/A is denoted under VCCO column, so if you follow the Notes(1)  you are good to go

 

LVDS_Support.png

 

 

LVDS Output signals from FPGA depends on VCCO but inputs can be any VCCO from 1.5 to 3.3V in HR banks under following conditions

 

LVDS_Support_Notes.png

 

Hope this clarifes

 

Regards,

Vanitha

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Xilinx Employee
Xilinx Employee
14,355 Views
Registered: ‎02-06-2013

Hi

 

Check below link

http://forums.xilinx.com/t5/7-Series-FPGAs/Artix-7-LVDS-Clock-Input-HR-Bank-with-VCCO-1-8V/td-p/435592

Regards,

Satish

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Visitor
Visitor
14,351 Views
Registered: ‎09-14-2011

Dear Sir,

 

Thanks for reply.

I have seen that post. In that input signal is 2.5 V but VCCo of artix is 1.8V. That configuration is fine but in my case ADC o/p itself is 1.8 V LVDS and that is directly connected to ARTIX with VCCO of 1.8V. So whether my configuration is correct??

 

 

Regards

Amit

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Scholar
Scholar
14,324 Views
Registered: ‎11-09-2013

the reply in that link doesnt tell it all - the poster says that 1.5V VCCIO is also ok for LVDS input, but this may not always be true, if the driver has 1.25V common mode, then LVDS signal may swing very close to 1.5V already :(

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Scholar
Scholar
14,321 Views
Registered: ‎11-09-2013

as long as your driver does not drive above 1.8V too much you are safe.

 

 

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Xilinx Employee
Xilinx Employee
14,320 Views
Registered: ‎07-11-2011

Hi

 

Your configuration should be fine when the conditions listed in below link discussion are satisfied

http://forums.xilinx.com/t5/7-Series-FPGAs/K7-problem-of-HR-BANK-LVDS-signals-selected/m-p/520449#M6507

 

 

Regards,

Vanitha

 

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Xilinx Employee
Xilinx Employee
14,296 Views
Registered: ‎07-31-2012

Hi,

 

On your questions

"I have connected ADC 1.8V LVDS output to ARTIX7 FPGA but ARTIX7 has only HR banks.

So whether can i operate ARTIX7 with 1.8V LVDS input""

 

Why can't you operating 1.8V lLVDS output from ADC to the 1.8V LVDS IO's of artix7. HR banks do support 1.8V signals. Why do you doubt that? Check UG471 if you need any clarification.

Thanks,
Anirudh

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Scholar
Scholar
14,290 Views
Registered: ‎11-09-2013

who said you cant?

 

just read ALL xilinx guides first..

and then second time and 3rd time.. :)

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Visitor
Visitor
14,281 Views
Registered: ‎09-14-2011

Dear Sir ,

 

Thanks for reply. As per UG471, they told like HR bank can be operated from 1.8 to 3.3 V but for LVDS mode you have to use 2.5V. Also they have mentioned that for 1.8V LVDS, it has to be connected to HP banks but in ARTIX7 we dont have HP banks.Thats why I got doubt.

 

Regards

Amit

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Scholar
Scholar
14,261 Views
Registered: ‎11-09-2013

no it does not say that.

 

it says that HP banks with max 1.8V VCCIO can also support LVDS.

 

not that 1.8V LVDS must be in  HP banks.

 

two different statements.

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Visitor
Visitor
10,856 Views
Registered: ‎09-14-2011

it means my configuration seams to be fine.

 

 

Regards

Amit

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Xilinx Employee
Xilinx Employee
10,852 Views
Registered: ‎07-11-2011

Hi,

 

Yes your configuration should work fine.

 

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Visitor
Visitor
10,851 Views
Registered: ‎09-14-2011

Dear Sir,

 

If you see table 1-43 in page89 of ug471, it says LVDS is available for HP banks only and LVDS-25 is available for HR bank only.

 

 

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Xilinx Employee
Xilinx Employee
17,700 Views
Registered: ‎07-11-2011

Hi,

 

It is true that LVDS 1.8 is in HP banks and LVDS_25 is in HR banks but if you see Table 1-55, N/A is denoted under VCCO column, so if you follow the Notes(1)  you are good to go

 

LVDS_Support.png

 

 

LVDS Output signals from FPGA depends on VCCO but inputs can be any VCCO from 1.5 to 3.3V in HR banks under following conditions

 

LVDS_Support_Notes.png

 

Hope this clarifes

 

Regards,

Vanitha

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Mark the post - "Accept as solution" and give kudos if information provided is helpful and reply oriented

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Visitor
Visitor
10,802 Views
Registered: ‎09-14-2011

Dear Vanitha,

 

Thnaks for the clarification.

 

 

Amit

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9,632 Views
Registered: ‎03-13-2015

Hi Amit,

              In continuation to your post I also in the phase of design of Artix 7 board and facing the same confusion. Plz answer the following: 

        1. Are you connecting VCCO 1.8v or 2.5v to that bank in which you are taking ADC (LVDS18) output? 

         2. Is your boad working fine with ADC value read by FPGA correctly?

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