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Observer
Observer
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Registered: ‎07-01-2019

LVDS 1 to 7 deserialization review

LVDS camalink 1 to 7 deserilazer is implemented based on XAPP585 with slight modification. Can someone review it and provide and suggestion whether this technique is good or bad and why?

 

serdes_1_to_7_mmcm_sdr.png

Here in this design PLL/MMCM is used for phase alignment instead of manually aligning it using delay primitive. So basically the sample clock is phase shifted by 180 degree as data and clock edge is aligned. And PLL/MMCM will keep this alignment. And once it's locked SERDES will use that clock to sample the data. As the clock is 180 degree out of phase so the edge of the clock is exactly at the center of the data (may eye opening).

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Moderator
Moderator
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Registered: ‎04-18-2011

Re: LVDS 1 to 7 deserialization review

I suspect that if you have 1 data line and 1 clock line then this will work well. 

The reason the XAPP has the delay line on the data is that there is a need to de-skew the data at a per-bit level if there is more than 1 data line if you want to acheive the highest data rates. 

Keith 

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Adventurer
Adventurer
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Registered: ‎06-05-2015

Re: LVDS 1 to 7 deserialization review

Dear proxidesai,

 

What FPGA are u going to use? There are fundamental differences between lets say the 7 series and a Spartan-6 concerning the usage of SERDES and IDELAYs.

The combination of an ISERDES with a PLL seems odd. Since the ISERDES will not output anything with a corresponding clock, u can't use the output of the ISERDES to drive the clock input of the PLL. And the PLL won't generate any clock without a valid and continuous clock input. In my opinion u should directly connect the IBUFDS to the PLL clock input using a BUFG. Or maybe adding an IDELAY to skew the clock as suggested in the answer record u mentioned. The data path seems plausible even though the word alignment must be connected to the data and not the clock.

Also be very careful with the clock rotation! Just because u shifted the clock by 180 degrees, does NOT mean the data is sampled in the middle of the eye, cuz the input delays may vary and also depend on temperature and votlage variations (which the timing analyzer takes into account). This means u will have to define correct input delay constraints to make sure that data is always captured within the valid area. This also defines the maximum achievable clock frequency. Also make sure to account for a non-perfect duty cycle (45/55 or worse).

Hope this helps a little.

 

Best regards,

Martin

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