07-02-2014 05:56 AM
My FPGA is XC7K325T-1FFG900I. About LVDS signals , It seems that there is only LVDS_25. Is it right?
If i set the HR bank 3.3V, the output pins of the bank can not output LVDS, Is it right?
07-02-2014 08:10 AM
That is correct. The VCCO of the HR banks for LVDS outputs (and inputs with DIFF_TERM) must be 2.5V. The XC7K325T also has HP banks where the LVDS outputs (and inputs with DIFF_TERM) must be 1.8V.
07-02-2014 05:48 PM
07-02-2014 06:29 PM - edited 07-02-2014 06:41 PM
Yes, the steps mentioned in AR can be a workaround to use LVDS variants in HP/HR Banks
11-04-2018 04:39 AM
HR bank voltage range is 1.8 to 3.3 volt and HP bank voltage range is 1.2 to 1.8 volt , no according to voltage you can select bank.