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Observer luganliuxi321
Observer
4,069 Views
Registered: ‎05-13-2013

LVDS_33 on HR bank?

Hi,

 

   My  FPGA is XC7K325T-1FFG900I.  About LVDS signals , It seems that there is only LVDS_25. Is it right?

 

   If i set the HR bank 3.3V, the output pins of the  bank can not output LVDS, Is it right?

  

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5 Replies
Xilinx Employee
Xilinx Employee
4,055 Views
Registered: ‎01-03-2008

Re: LVDS_33 on HR bank?

That is correct.  The VCCO of the HR banks for LVDS outputs (and inputs with DIFF_TERM) must be 2.5V.  The XC7K325T also has HP banks where the LVDS outputs (and inputs with DIFF_TERM) must be 1.8V. 

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Adventurer
Adventurer
4,049 Views
Registered: ‎02-16-2014

Re: LVDS_33 on HR bank?

But in this post,it says It is acceptable to have LVDS inputs in HP I/O banks even if the VCCO level is not 1.8V.

Similarly, it is acceptable to have LVDS_25 inputs in HR I/O banks even if the VCCO level is not 2.5V.

http://www.xilinx.com/support/answers/43989.html
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Xilinx Employee
Xilinx Employee
4,046 Views
Registered: ‎07-11-2011

Re: LVDS_33 on HR bank?

Hi,

 

Yes, the steps mentioned in AR can be a workaround to use LVDS variants in HP/HR  Banks

 

Regards,

Vanitha

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Adventurer
Adventurer
4,043 Views
Registered: ‎02-16-2014

Re: LVDS_33 on HR bank?

Got it ,thanks!
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Newbie rohitcif
Newbie
514 Views
Registered: ‎11-04-2018

Re: LVDS_33 on HR bank?

HR bank voltage range is 1.8 to 3.3 volt and HP bank voltage range is 1.2 to 1.8 volt , no according to voltage you can select bank.

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