cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
vivienwwp
Explorer
Explorer
946 Views
Registered: ‎10-28-2018

LVDS_CLK_P/N be routed to MRCC/SRCC or regular differential IOs?

Jump to solution

Hi,

   Do I route the LVDS_CLK_P/N differential pair to a MRCC/SRCC pair on the FPGA? Or is it ok to be routed to the regular differential IOs? 

If MRCC or SRCC is required, then should this be the MRCC or SRCC pins? 

 

Thanks

Vivien

0 Kudos
Reply
1 Solution

Accepted Solutions
pthakare
Moderator
Moderator
936 Views
Registered: ‎08-08-2017

Hi @vivienwwp

Are you bringing the clock onto the Device or  you are forwarding clock out from the device ?

If you are bringing the the clock onto the device then you need to use the CCIO (Clock capable inputs) . Every 7 series FPGA has four clock-capable inputs in each bank. Two of the four are Multi-Region Clock Capable (MRCC) and the other two are Single Region Clock Capable (SRCC). These inputs are regular I/O pins with dedicated connections to internal clock resources 

SRCCs access a single clock region and the global clock tree, as well as other CMTs above and below in the same column

SRCCs can drive

  • Regional clocks lines (BUFR, BUFH, BUFIO) within the same clock region
  • CMTs in the same clock region and adjacent clock regions
  • Global clocks lines (BUFG) in the same top/bottom half of the device

MRCCs can access multiple clock regions and the global clock tree MRCCs function the same as SRCCs and can additionally drive multi-clock region buffers (BUFMR) to access up to three clock regions.

if you are forwarding clock out from the device, then you can use any regular IOs,  I.e 

Clock path is 

Clock you want to forward -> ODDR -> OBUFDS ->Routed to any regular differential pair . The ODDR usage in the clock path is explained in detail by @avrumw  in the below Similar post.

https://forums.xilinx.com/t5/7-Series-FPGAs/Clock-capable-pin-pair-as-input-and-output/m-p/900002#M29713

---------------------------------------------------------------------------------------------------------------------------------------------------------

Reply if you have any queries, Give Kudos and accepts as solution

---------------------------------------------------------------------------------------------------------------------------------------------------------

-------------------------------------------------------------------------------------------------------------------------------------------------------

 

 

 

 

 

 

 

 

-------------------------------------------------------------------------------------------------------------------------------
Reply if you have any queries, give kudos and accept as solution
-------------------------------------------------------------------------------------------------------------------------------

View solution in original post

2 Replies
pthakare
Moderator
Moderator
937 Views
Registered: ‎08-08-2017

Hi @vivienwwp

Are you bringing the clock onto the Device or  you are forwarding clock out from the device ?

If you are bringing the the clock onto the device then you need to use the CCIO (Clock capable inputs) . Every 7 series FPGA has four clock-capable inputs in each bank. Two of the four are Multi-Region Clock Capable (MRCC) and the other two are Single Region Clock Capable (SRCC). These inputs are regular I/O pins with dedicated connections to internal clock resources 

SRCCs access a single clock region and the global clock tree, as well as other CMTs above and below in the same column

SRCCs can drive

  • Regional clocks lines (BUFR, BUFH, BUFIO) within the same clock region
  • CMTs in the same clock region and adjacent clock regions
  • Global clocks lines (BUFG) in the same top/bottom half of the device

MRCCs can access multiple clock regions and the global clock tree MRCCs function the same as SRCCs and can additionally drive multi-clock region buffers (BUFMR) to access up to three clock regions.

if you are forwarding clock out from the device, then you can use any regular IOs,  I.e 

Clock path is 

Clock you want to forward -> ODDR -> OBUFDS ->Routed to any regular differential pair . The ODDR usage in the clock path is explained in detail by @avrumw  in the below Similar post.

https://forums.xilinx.com/t5/7-Series-FPGAs/Clock-capable-pin-pair-as-input-and-output/m-p/900002#M29713

---------------------------------------------------------------------------------------------------------------------------------------------------------

Reply if you have any queries, Give Kudos and accepts as solution

---------------------------------------------------------------------------------------------------------------------------------------------------------

-------------------------------------------------------------------------------------------------------------------------------------------------------

 

 

 

 

 

 

 

 

-------------------------------------------------------------------------------------------------------------------------------
Reply if you have any queries, give kudos and accept as solution
-------------------------------------------------------------------------------------------------------------------------------

View solution in original post

vivienwwp
Explorer
Explorer
924 Views
Registered: ‎10-28-2018

Thanks! This is helpful.

0 Kudos
Reply