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Observer
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Registered: ‎07-18-2019

LVDS SERDES Reference Design

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Hello. Im am using the XAPP1315 Reference Design to implement a 7:1 serdes interface for video processing.

My parallel input is clocked at 25 MHz, so that the VCO frequency generated from the MMCM instantiated by the design is 175MHz. The frequency range for the MMCM VCO appears to be from 600 to 1600 MHz, so that my frequency is not allowed, issuing an error during simulation. In trasmission (serializer) I was able to overcome this issue by modifying the VCO_MULTIPLIER parameter, changing the default to an higher value.

On the receiver side the same operation cannot be done, because the value of VCO_MULTIPLIER is hardcoded into a FSM which handles delay and synchronization. If I try to do the same the ouput is not synchronized and the deserializer does not work as intended. I guess I am supposed to modify the FSM (and consequently the delay value) to match my VCO_MULTIPLIER value, but there is no documentation about that.

I expected the reference design to be configurable in order to work with different input frequencies, but from what I can see that is not the case.

Is there some documentation I didn't find about that or am I supposed to figure it out myself by trial and error?

Thanks is advance for the help

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Moderator
Moderator
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Registered: ‎08-08-2017

Hi @giacomo.gloria 

End objective here is to have 1:7 deserialization for video application, which can be implemented using ISERDESE3 which support 1:4, 1:8  deserialization and gearbox for 8:7 conversion.

Application note XAPP1315 provides the ready design for this usage but the supported data range is 415 Mb/s up to 1,100 Mb/ and for lower data rate you need to implement your own design using IDELAYE3 and ISRDESE3 primitives.

Application note XAPP1324 describes the recommended usage models and timing analysis methodologies that can be used for I/O interfaces using component mode primitives (ODDRE1, IDDRE1, ISERDESE3, and OSERDESE3).

User guide UG571 starting from page 161 have the port and attribute details of ISERDESE3 and IDELAYE3 which are used in application note 1315.

The primitive instantiation is given in language template and library user guide starting from page 390

https://www.xilinx.com/support/documentation/sw_manuals/xilinx2019_1/ug974-vivado-ultrascale-libraries.pdf

I hope this helps to move forward

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Moderator
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Registered: ‎08-08-2017

Hi @giacomo.gloria 

End objective here is to have 1:7 deserialization for video application, which can be implemented using ISERDESE3 which support 1:4, 1:8  deserialization and gearbox for 8:7 conversion.

Application note XAPP1315 provides the ready design for this usage but the supported data range is 415 Mb/s up to 1,100 Mb/ and for lower data rate you need to implement your own design using IDELAYE3 and ISRDESE3 primitives.

Application note XAPP1324 describes the recommended usage models and timing analysis methodologies that can be used for I/O interfaces using component mode primitives (ODDRE1, IDDRE1, ISERDESE3, and OSERDESE3).

User guide UG571 starting from page 161 have the port and attribute details of ISERDESE3 and IDELAYE3 which are used in application note 1315.

The primitive instantiation is given in language template and library user guide starting from page 390

https://www.xilinx.com/support/documentation/sw_manuals/xilinx2019_1/ug974-vivado-ultrascale-libraries.pdf

I hope this helps to move forward

-------------------------------------------------------------------------------------------------------------------------------
Reply if you have any queries, give kudos and accept as solution
-------------------------------------------------------------------------------------------------------------------------------

View solution in original post

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