01-09-2020 11:37 AM - edited 01-12-2020 02:02 AM
I interfaced FPGA(Kintex_7, LVDS_25, Vadj=1.8v)with external board to provide inputs(Analog voltage and reference voltage) to LVDS. I adjusted frequencies of signal generators to 1µHz and amplitudes to least possible value 10mv. When both the inputs are 10mv, comparator output is zero. I kept analog voltage 10mv and kept on increasing reference voltage. When Vref was increased to 51mv, the comparator output became 1. In the next step, reference voltage(51mv) is kept same and analog voltage is increased till comparator output became 0. This process is repeated to max input voltage levels. Please find the attached file for the values noted down. If you can notice from the file, the analog voltage is always less than Reference voltage but still the comparator keeps switching ON and OFF (toggle). I'm not able to understand this behaviour. In the beginning, the comparator output toggles when the difference between analog and reference voltage is 41mv (51mv - 10mv). But as i go on increasing the analog and reference voltages, the voltage difference for which the comparator output toggles, is increasing to 100mv, 250mv and so on, as seen in the file. I fail to understand the reason for this. According to my understanding, the input voltage (Vref and Vana) difference for comapartor output to toggle, should always remain constant, even if i'm increasing the input voltage values. But as said above, the difference doesn't remain constant, but increasing as well. Hence, it would be helpful if someone can explain the LVDS input output behavior as a comparator considering those noted values in the attached file.
01-10-2020 11:28 AM
First let’s look at LVDS_25 specs from Table 12 of the Kintex-7 datasheet (DS182). Note that for an LVDS_25 input, the common mode voltage, VICM, should between 0.300 and 1.500 V. Also, the differential input voltage, VIDIFF, should be between 0.100 and 0.600 V. So, during your test, when the voltage inputs to the LVDS_25 gate are outside of these specifications then anything can happen.
However, and perhaps most importantly, the LVDS_25 gate is digital logic and should not be thought of as a comparator. That is, when the Q-input is at least 0.100V more than the nQ-input then the gate output is guaranteed to be in one state. When the nQ-input is at least 0.100V more than the Q-input then the gate output is guaranteed to be in the other state. When the difference between the Q-input and the nQ-input is less than 0.100V then you are in an undefined region where anything can happen.
This same thing happens with ordinary LVTTL logic that has thresholds of about 0.8V and 2.0V. If you feed a voltage that is between 0.8V and 2.0V to the LVTTL gate then the output of the gate could be anything. In fact, it could oscillate between and high and low states as noise causes the input voltage to move around in the undefined region between 0.8V and 2.0V.
Thus, for proper operation of logic (whether it is LVTTL or LVDS_25), it is important that inputs to the gate have fast transitions through the undefined region.
01-13-2020 04:42 AM
01-13-2020 08:49 AM - edited 01-13-2020 08:51 AM
Only when Vref was made 183mv, the comp output became 0. I fail to correlate this with my theoretical understanding.
When Vref=183mV and Vana=75mV the magnitude of (Q-nQ) is 108mV, which is very close to VIDIFF(min)=100mV for LVDS. Perhaps there is measurement error or voltage drops that cause your 108mV reading to actually be less than 100mV. Also, as shown below, these values for Q and nQ violate the VICM specification for LVDS.
Also, I don't find in the datasheet, what should be the minimum Q and nQ input values..
The datasheet LVDS specifications for VICM=(Q+nQ)/2 and VIDIFF=mag(Q-nQ) work together to restrict the range of Q and nQ. For example, if (Q-nQ)=100mV and you restrict (Q+nQ)/2>300mV then you have two equations in the two unknowns, (Q and nQ) . For this example, the solution is Q>350mV and nQ>250mV. All combinations of [VICM>300mV, VICM<1500mV, VIDIFF>100mV, and VIDIFF<600mV ] can be analyzed in this way to find the voltage restrictions for Q and nQ.
01-13-2020 09:07 AM
01-13-2020 09:13 AM
01-16-2020 09:08 AM
I now understood how are the input voltage ranges are derived, using the spec. But i have another related query. As you can see from my file, as Vana (Q) increases Vref (Qn) also increases, but not to the same extent but more. I mean to say, that as Q increases, Vidiff also increases. Just to be precise :
Vana : 250, 275, 300, 325, .....
Vref (for the LVDS to work as comparator) : 529, 577, 625, 674, ...
Means, Vdiff : 279, 302, 325, 349.... and so on..
Is there any reason for Vdiff to increase as the input voltages increase ?
01-16-2020 10:24 AM
01-16-2020 04:13 PM
I believe that your test method is giving you false measurements for VIDIFF of the LVDS_25 gate.
As I mentioned before, it is important for inputs to LVDS_25 logic to have fast transitions through the undefined region (ie. when VIDIFF < 100mV).
Here is another way to do the testing that should give better results.
01-22-2020 08:14 AM
I think the values are incorrect. So, I thought to take new values considering LVDS_specs.
1. I need to check LVDS input output behaviour for D.C. I'm using two signal generators to give inputs to LVDS_25. I will set the frequencies of both signals to 1µHz. Now, what should be the minimum amplitude and offset voltage for positive pin of LVDS and negative pins of LVDS_25 i.e., from which value should I start measurement?. Also, should I follow the same procedure which I described in first question? (In first step Voltage(amplitude+offset) of one signal(positive pin) is kept constant and the other signal(negative pin) is varied till LVDS toggle. In second step,
negative pin signal is kept constant and positive pin signal is varied.
Could you please explain how to check the if LVDS_25 can be used as a comparator?
01-22-2020 09:06 AM