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Registered: ‎06-28-2019

LVDS as a comparator

I want to use LVDS as a comparator for the analog input in HP bank. The analog input is sent to Vp, and Vn is used as a threshold=900mV. And I want to know whether the propagation delay between the input and the output can keep stable when the slew rate and the overdrive voltage are greater than a certain value. So I used a signal generator (Agilent 81134A) to generate a pulse with following parameters:

V_low = 800mV

V_high = 1000mV, 1100mV...1800mV

V_high_pulse_width = 12ns

Signal Period = 260ns

Rise time = 80ps (from datasheet in Agilent 81134A and I also see the fast rise edge in oscilloscope)

I sent above waveforms to FPGA-LVDS, then use LVCMOS18-F-12 (HP bank) output to an oscilloscope.

I found that the propagation delay of LVDS change about 400ps when V_high is set from 1000mV to 1800mV. Even when V_high is higher than 1400mV, if I set V_high to be higher, the propagation delay will still be smaller.

From my test I can't find a propagation delay stable region when the slew rate and overdrive voltage are greater than a certain value, does that make sense?

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Registered: ‎04-26-2015

I can't comment on most of this - but it's worth noting that at anything above 1500mV you're outside the allowed specs for LVDS input (600mV V_IDIFF maximum). You're not outside the absolute maximum ratings so you won't do any damage, but there is also no guarantee that the input will behave according to the datasheet specs here.

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Registered: ‎01-22-2015

wubo123@mail.ustc.edu.cn 

As u4223374 says, your test setup has violated some of the specifications for LVDS, which are (from Table 13 in DS182(v2.18)):

Differential Input Voltage, VIDIFF = 100-600 mV = mag(V_high – V_low)
Common-Mode Input Voltage, VICM = 300-1425 mV = (V_high + V_low)/2

Note that when V_high=V_low=800mV then you are in the forbidden region  (VIDIFF<100mV) of LVDS logic, where anything can happen.  The LVDS output may even oscillate!  So, your test setup can be improved by fixing V_low at 800mV and switching V_high between some voltage less than 700mV and some voltage higher than 900mV – while still satisfying VDIFF and VICM specifications of LVDS.

Finally, when going from LVDS input to LVCMOS18 output, the signal must pass through IBUFDS and OBUF buffers of the FPGA.  From Table 21 of DS182, the OBUF delay, TIOOP, is at least 1260ps for LVCMOS18_F12.  However, OBUF delay is process/voltage/temperature (PVT) dependent, varying (rule-of-thumb) by 3:1.  That is, the OBUF delay could vary between 420ps and 1260ps over PVT.   So, your test setup could show quite a lot of variation (over PVT) in the propagation delay of the signal as it passes through the FPGA.

Cheers,
Mark