06-01-2018 05:04 AM
I'm new to FPGA so please any help will be appreciated.
I have a project to design a high speed communication (100 - 200 MHz) between two spartan 6 FPGA. There is only a LVDS data channel between them. the data is Ethernet frames. I have been reading several documentation and my idea is to use SERDES in both FPGAs. My questions are:
1- How to generate the clock in both FPGA?
2- How the receiver will know that the transmitter want to transmit if there is no control signal?
3- I read all the discussions about Bitslip in the forum but could not understand it that much. Do I need to use bitslip?
4- is there any other way to achieve 100 - 200 MHz communication between two FPGA?
Thanks in advance
06-01-2018 07:52 AM
1) You can't
2) You coding
Ok, lots of big open questions,
e.g. Bit slip is a way of synchronising data, its not a need , but a way.
I'd concentrate on big questions first,
First question, how to get data between the two fpgas ?
have a search on that, you will find lots of solutions.
let us know what you find
06-09-2018 07:03 AM - edited 06-09-2018 07:06 AM
Thanks for your response.
Most of the application note that address SERDES are for source synchronous system. For now, I checked xapp224 and xapp225.
I'm thinking about using blind oversampling CDR because honestly, I couldn't understand how to implement CDR using PLL.
Now I'm reading about the best algorithm for blind oversampling and try to understand how to use the training sequence.
I would like to know more about SERDES and how to use bitslip and actually use them but the problem that I'm super limited in time because I have to finish my thesis in mid of July. if you know any reference or book talk about it please let me know.
My confusion about how the receiver will recognize the beginning of the frame is still not solved. I know that I should send some marker to indicate the beginning of the frame and the end of it but or count the data if the length is known or use the preamble of the Ethernet frame as a training sequence. I'm familiar with UART design like start and stop bit but never worked with high-speed communication.
06-09-2018 08:06 AM
Whats your thesis ?
is it on implementing bitslip / oversampling ,
You already know how to do oversampling and start detect.
Most Uarts are 16 times over sampled,
and use the start edge to detect when to time form to find the middle of each data bit.