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Bareil761
Visitor
Visitor
247 Views
Registered: ‎06-04-2020

LVDS in HR bank

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Hi all,

I have an ADC which needs 1.8V supply. I also have a xc7z014, which has no HP banks and thus no LVDS (1.8V) compatible pins with internal termination. Since I am on a Trenz board where I cannot add external termination resistor I cannot use the LVDS_25 while being 1.8V powered and still use termination resistor.

However, can I power my HR bank with a 2.5V, use "DIFF_TERM true" and still communicate correctly with the ADC powered from 1.8V? From what I gathered, the LVDS_25 and LVDS (1.8V) have the same voltages.

 

 

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bpatil
Xilinx Employee
Xilinx Employee
97 Views
Registered: ‎03-07-2018

Hi @Bareil761 

I agree with @bruce_karaffa suggestion.

Typically, LVDS IO standard is independent from VCCO;  but in case of Xilinx FPGA internal termination resistor and DC Biasing makes it dependent on VCCO.

If you observe carefully in Table 18: LVDS_25 DC Specifications and Table 19: LVDS DC Specifications provided in DS923-virtex-ultrascale-plus - Page 17 , LVDS VICM and VDIFF parameters matches to each other. (Note: For ease in understanding suggested to refer Virtex US+ datasheet instead of Zynq7000 ;as Virtex US+ device supports both LVDS and LVDS_25 IO standard)

So, you can provide LVDS input to FPGA with considering guidelines provided in AR# 43989. Please check LVDS interface checklist provided in AR# 43989 and verify your interface.

Regards,
Bhushan

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bruce_karaffa
Scholar
Scholar
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Registered: ‎06-21-2017

Both LVDS25 and LVDS18 implement the LVDS electrical standard if powered by the correct voltage.  You can use the HR bank powered by 2.5V to communicate with a chip that uses LVDS.  You can use the internal termination resistors in this case.

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bpatil
Xilinx Employee
Xilinx Employee
98 Views
Registered: ‎03-07-2018

Hi @Bareil761 

I agree with @bruce_karaffa suggestion.

Typically, LVDS IO standard is independent from VCCO;  but in case of Xilinx FPGA internal termination resistor and DC Biasing makes it dependent on VCCO.

If you observe carefully in Table 18: LVDS_25 DC Specifications and Table 19: LVDS DC Specifications provided in DS923-virtex-ultrascale-plus - Page 17 , LVDS VICM and VDIFF parameters matches to each other. (Note: For ease in understanding suggested to refer Virtex US+ datasheet instead of Zynq7000 ;as Virtex US+ device supports both LVDS and LVDS_25 IO standard)

So, you can provide LVDS input to FPGA with considering guidelines provided in AR# 43989. Please check LVDS interface checklist provided in AR# 43989 and verify your interface.

Regards,
Bhushan

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Give Kudos to a post which you think is helpful and reply oriented.
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