UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Highlighted
Visitor yere1
Visitor
1,376 Views
Registered: ‎03-05-2018

LVDS in spartan 6 XC6SLX45, package CSG324

I'm trying to get ANY signal on the HDMI output in J2. I use the code below, but cannot see anything when scoping (it's all 0v).

Below is my module and ucf:

Module:

module YE_spartan6_v002(

	//--General
	input CLK_IN1,		

	//--ASK
	output oASKp,
	output oASKn
	);
	OBUFDS OBUFDS_inst (
		.O(oASKp), // 1-bit output: Diff_p output (connect directly to top-level port)
		.OB(oASKn), // 1-bit output: Diff_n output (connect directly to top-level port)
		.I(1) // 1-bit input: Buffer input
	);

endmodule

 

.ucf file:

# CLK
NET "CLK_IN1" LOC = L15;

# ASK

# PlanAhead Generated IO constraints 
NET "oASKp" IOSTANDARD = LVDS_25;
# PlanAhead Generated physical constraints 
NET "oASKp" LOC = C7;
NET "oASKn" LOC = A7;

 

Am I doing something wrong?

Tags (2)
0 Kudos
4 Replies
1,316 Views
Registered: ‎06-21-2017

Re: LVDS in spartan 6 XC6SLX45, package CSG324

Do you have a terminating resistor between the p and n signals?

0 Kudos
Visitor yere1
Visitor
1,244 Views
Registered: ‎03-05-2018

Re: LVDS in spartan 6 XC6SLX45, package CSG324

Yes I'm using a terminating resistor.

0 Kudos
Community Manager
Community Manager
1,230 Views
Registered: ‎08-08-2007

Re: LVDS in spartan 6 XC6SLX45, package CSG324

As the input to the OBUFDS is 1 I'm wondering if ISE has removed it? 

If you look in FPGA Editor is the OBUFDS still there?

What else is in the bank with the oASKp/n pins? Are they behaving as expected?

-------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------
0 Kudos
Xilinx Employee
Xilinx Employee
1,166 Views
Registered: ‎06-30-2010

Re: LVDS in spartan 6 XC6SLX45, package CSG324

as @sandrao mentions, the SW could have removed it. Have a look at the NCD file to verify the '1' is still there, you could also try adding a VIO from chipscope to allow you to control it. or you could route a pushbutton from an input to the output you are trying to measure
-------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------
0 Kudos