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Newbie
Newbie
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Registered: ‎04-18-2019

LVDS input timing spec of Spartan 7

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Hi Xilinx support team,

We are currently implementing "LVDS conversion to MIPI" (LVDS input, MIPI HS & LP output) on a Spartan 7 FPGA.

Could you tell me where I can find the LVDS input timing specs, especially setup & hold time?

Is it the one listed in Table 23 of DS189 document?

 

Sincerely,

Simon

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Mentor
Mentor
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Registered: ‎02-24-2014

Those are the nominal setup/hold times, but in the absence of other timing paths, they don't mean much.   You need to set an input timing constraint and run a timing analysis to actually see this being applied in context.

Read Chapter 5 of UG906, and all things shall become clear.

 

Don't forget to close a thread when possible by accepting a post as a solution.

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Mentor
Mentor
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Registered: ‎02-24-2014

Those are the nominal setup/hold times, but in the absence of other timing paths, they don't mean much.   You need to set an input timing constraint and run a timing analysis to actually see this being applied in context.

Read Chapter 5 of UG906, and all things shall become clear.

 

Don't forget to close a thread when possible by accepting a post as a solution.

View solution in original post

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Teacher
Teacher
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Registered: ‎07-09-2009
LVDS is just a voltage e/ current specification, it has no timming informaotin.
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Teacher
Teacher
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Registered: ‎07-09-2009

You need to either as mentioned, use th etools,

 

or by hand, add the LVDS propergation delay from the tables, to the routing dleay for th erout you want to use, to the setup time of the register you want to use, allowing for the clock route...

 

Stay with the tools,,

Rember, the tools meet your spec and stop,

    so you need to put a timming constraint on to see if you meet timing,

        no constraint and you get what ever the tool stoped at.

 

 

<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>
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