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Observer john
Observer
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Registered: ‎05-17-2018

LVDS pins before configuration

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Hi, I am interfacing a zynq FPGA with another device with a source-synchronous LVDS link from a HR iobank.

My problem is that the maximum voltage allowed at any digital input of said device is 1.8V, while my development FPGA board has VCCO set to 2.5 and the PUDC_B pin tied to ground. This means that before and during FPGA configuration the LVDS lines actually output a 2.5 signal which is potentially damaging for the device.

What is the best/standard solution for this case? should I add an external pulldown to the LVDS line or maybe employing an AC coupling?

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Scholar brimdavis
Scholar
777 Views
Registered: ‎04-26-2012

Re: LVDS pins before configuration

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@john   "What is the best/standard solution for this case? should I add an external pulldown to the LVDS line or maybe employing an AC coupling?"

Some of the I/O protection ESD diode arrays come in low capacitance versions suitable for LVDS, and with a diode configuration that clamps to the supply rails; they are usually called "low capacitance rail clamps" or a similar name, e.g. something like this one from OnSemi:

   https://www.onsemi.com/pub/Collateral/NUP4301MR6T1-D.PDF

Installing these on your 1.8V device's LVDS inputs would clamp any pullup voltage from an unconfigured FPGA pin to one diode drop above the 1.8V rail.

-Brian

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8 Replies
796 Views
Registered: ‎01-22-2015

Re: LVDS pins before configuration

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Hi John,

You'd think there was a LVDS-3.3V to LVDS-1.8V convertor/buffer out there - but I haven't found it. 

LVDS-3.3V to LVCMOS(single-end)-1.8V convertors are available (see SNLA307).  Use of these in some fashion might be the cleanest solution to the problem.

As you mentioned, AC-coupling and a handful of resistors (eg. see Fig. 6 in SLLA101) can be used to convert the Vcm and Vdiff of LVDS-3.3V to what you need for LVDS-1.8V.  However, I don’t think this method can be used when translating from LVDS-1.8V to LVDS-3.3V.

Cheers,
Mark

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Scholar drjohnsmith
Scholar
786 Views
Registered: ‎07-09-2009

Re: LVDS pins before configuration

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Is your LVDS differential ?
can it be encoded such that it has 'zero dc' . such as manchester encoding ?
if so, then AC coupling works just fine, the receivers if I remember correctly will put their Vcm in the right place. and LVDS is happy with the Vdiff.

this might help or confuse...

https://www.xilinx.com/support/answers/43989.html

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Scholar brimdavis
Scholar
778 Views
Registered: ‎04-26-2012

Re: LVDS pins before configuration

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@john   "What is the best/standard solution for this case? should I add an external pulldown to the LVDS line or maybe employing an AC coupling?"

Some of the I/O protection ESD diode arrays come in low capacitance versions suitable for LVDS, and with a diode configuration that clamps to the supply rails; they are usually called "low capacitance rail clamps" or a similar name, e.g. something like this one from OnSemi:

   https://www.onsemi.com/pub/Collateral/NUP4301MR6T1-D.PDF

Installing these on your 1.8V device's LVDS inputs would clamp any pullup voltage from an unconfigured FPGA pin to one diode drop above the 1.8V rail.

-Brian

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Observer john
Observer
689 Views
Registered: ‎05-17-2018

Re: LVDS pins before configuration

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Think you for your answers,

markg@prosensing.com , I didn't know there was a difference between "LVDS3.3" and "LVDS1.8",  I thought it was just matter of the VCCO used on Xilinx FPGAs. Anyway I don't have any issue with the FPGA lvds output, the problem is just that during (and before) configuration the output is not LVDS.

@drjohnsmith , yes it does use manchester encoding, but for AC coupling the receiver doesn't apply any internal bias so I would have to add an external bias to restore the common mode. I forgot to mention that the link is bidirectional (3-state) so I guess I would need a bias circuit on both sides.

@brimdavis , well we were considering to add some additional ESD protection anyway, so this seem to be the best solution in this case.

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Scholar drjohnsmith
Scholar
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Registered: ‎07-09-2009

Re: LVDS pins before configuration

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if the input is a Xilinx FPGA, in LVDS mode, then its self biasing to its mid point.

do no tuse external bias network on LVDS inputs if AC coupling.

 

 

 

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Observer john
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Registered: ‎05-17-2018

Re: LVDS pins before configuration

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ok, thanks for the tip @drjohnsmith . ug471 shows an external biasing circuit on an LVDS input (page 93 fig. 1-72), I am assuming the internal bias is enabled only when DIFF_TERM=true, am I wrong?

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Scholar drjohnsmith
Scholar
658 Views
Registered: ‎07-09-2009

Re: LVDS pins before configuration

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Well,

 

Im having a bad day me thinks,

 

that app note says use bias, 

I am blown away,  as I have seen many many designs for clock inputs that are ac coupled and not biased and work just fine.   Im now wondering if w ehave ever meassured the bias voltage when its AC coupled.

 

Thank you for this.

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Scholar brimdavis
Scholar
636 Views
Registered: ‎04-26-2012

Re: LVDS pins before configuration

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@john   " I am assuming the internal bias is enabled only when DIFF_TERM=true, am I wrong?"

The original V2 era LVDS_25_DCI was implemented with split terminations, which self-biased to VCCO/2 .

The follow-on Xilinx LVDS input terminations did not use the split termination technique, and required external bias for AC coupling.

Some of the newer parts now support internal bias, dependent upon the family, I/O bank type, and VCCO;  e.g.  DQS_BIAS (Ultrascale HP) , or  EQUALIZATION = EQ_LEVEL0_DC_BIAS (Ultrascale HR); V6 and V7 might also support something along those lines, I don't recall offhand.

In general, if you can find a split termination differential standard that works with your input swing, you can AC couple into that without external bias.

-Brian