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Observer goldmanggo
Observer
1,017 Views
Registered: ‎01-05-2018

LVDS signal connected to HR Bank which powered in 1.8V

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I have a design shown as the picture below.

In a HR bank powered by 1.8v supply, several LVDS differential signals are used. But, in vivado or ise constraint file i can't define them like ‘IOSTANDARD = LVDS', or it will be an error. Finally, i use the 'LVDS_25' constraint, and it passed and worked well. However, does that damage  the FPGA device? is there any performance degradation?

k7_lvds.PNG

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Scholar drjohnsmith
Scholar
1,200 Views
Registered: ‎07-09-2009

Re: LVDS signal connected to HR Bank which powered in 1.8V

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setting the standard to _25 is fine for an input.

 

LVDS is in theory a 'standard' voltage swing around a reference level, that fixed for all lvds ,

 

this might help

 

https://www.xilinx.com/support/answers/43989.html

 

 

 

<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>

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Scholar jmcclusk
Scholar
1,076 Views
Registered: ‎02-24-2014

Re: LVDS signal connected to HR Bank which powered in 1.8V

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If these are inputs, this is fine, with the following caveats (from UG471):

 

It is acceptable to have differential inputs such as LVDS and LVDS_25 in I/O banks that are
powered at voltage levels other than the nominal voltages required for the outputs of those
standards (1.8V for LVDS outputs, and 2.5V for LVDS_25 outputs). However, these criteria
must be met:
• The optional internal differential termination is not used (DIFF_TERM = FALSE,
which is the default value).
• The differential signals at the input pins meet the VIN requirements in the
Recommended Operating Conditions table of the specific device family data sheet.

 

In short,  LVDS inputs are fine, as  long as you don't use the internal termination.   For LVDS outputs, there will probably be degraded speed characteristics (i.e. slew rates), but it won't damage the device.    If you need really high speed, you might want to consider changing to another differential standard.

Don't forget to close a thread when possible by accepting a post as a solution.
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Scholar drjohnsmith
Scholar
1,201 Views
Registered: ‎07-09-2009

Re: LVDS signal connected to HR Bank which powered in 1.8V

Jump to solution

setting the standard to _25 is fine for an input.

 

LVDS is in theory a 'standard' voltage swing around a reference level, that fixed for all lvds ,

 

this might help

 

https://www.xilinx.com/support/answers/43989.html

 

 

 

<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>

View solution in original post

Observer goldmanggo
Observer
936 Views
Registered: ‎01-05-2018

Re: LVDS signal connected to HR Bank which powered in 1.8V

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Thanks a lot , that's exactly what i want!

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