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Visitor
Visitor
7,489 Views
Registered: ‎04-28-2014

LVDS sys clock on VC707

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Hi,

I'm implementing a simple VHDL program using for a VC707 eval board and have difficulties to use the system clock.

The clock is a LVDS 200 Hz clock. I have defined the SYSCLK_P/_N pins in the XDC file. It is needed to instantiate differential input and output buffers in the code.

Do you know how I can instantiate a LVDS buffer in a VHDL code ?

Thanks foryour help, Olivier

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Scholar
Scholar
11,108 Views
Registered: ‎06-14-2012

IBUFDS_inst: IBUFDS
 generic map (--DIVISOR => 2604,
   DIFF_TERM => TRUE, -- Differential Termination
   IBUF_LOW_PWR => TRUE, -- Low power (TRUE) vs. performance (FALSE) setting for referenced I/O standards
   IOSTANDARD => "DEFAULT"
  )
  port map (
 O => sys_clk, -- Buffer output
 I => sys_clk_p, -- Diff_p buffer input (connect directly to top-level port)
 IB => sys_clk_n -- Diff_n buffer input (connect directly to top-level port)
  );

 

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Scholar
Scholar
11,109 Views
Registered: ‎06-14-2012

IBUFDS_inst: IBUFDS
 generic map (--DIVISOR => 2604,
   DIFF_TERM => TRUE, -- Differential Termination
   IBUF_LOW_PWR => TRUE, -- Low power (TRUE) vs. performance (FALSE) setting for referenced I/O standards
   IOSTANDARD => "DEFAULT"
  )
  port map (
 O => sys_clk, -- Buffer output
 I => sys_clk_p, -- Diff_p buffer input (connect directly to top-level port)
 IB => sys_clk_n -- Diff_n buffer input (connect directly to top-level port)
  );

 

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Xilinx Employee
Xilinx Employee
7,483 Views
Registered: ‎08-02-2007

Hi,

 

Refer to the code available in page 171 of this document

 

http://www.xilinx.com/support/documentation/sw_manuals/xilinx13_4/7series_hdl.pdf

 

Library UNISIM;
use UNISIM.vcomponents.all;
-- IBUFGDS: Differential Global Clock Input Buffer
-- 7 Series
-- Xilinx HDL Libraries Guide, version 13.4
IBUFGDS_inst : IBUFGDS
generic map (
DIFF_TERM => FALSE, -- Differential Termination
IBUF_LOW_PWR => TRUE, -- Low power (TRUE) vs. performance (FALSE) setting for referenced I/O standards
IOSTANDARD => "DEFAULT")
port map (
O => O, -- Clock buffer output
I => I, -- Diff_p clock buffer input (connect directly to top-level port)
IB => IB -- Diff_n clock buffer input (connect directly to top-level port)
);
-- End of IBUFGDS_inst instantiation

 

--Hem

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Xilinx Employee
Xilinx Employee
7,469 Views
Registered: ‎07-31-2012

Hi,

 

In addition you can also use the selectio wizard to generate the code for input/output single_ended/differential buffers for data and clock for verilog/vhdl.

Thanks,
Anirudh

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Xilinx Employee
Xilinx Employee
7,467 Views
Registered: ‎08-01-2012

Please refer the below link document which has all coding templates including LVDS buffer in VHDL code

http://www.xilinx.com/support/documentation/sw_manuals_j/xilinx14_7/7series_hdl.pdf

________________________________________________

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Highlighted
5,395 Views
Registered: ‎03-12-2015
Can I use this clock as GTXrefclock or Init click by using DCM(Clock management)?
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Xilinx Employee
Xilinx Employee
5,323 Views
Registered: ‎02-06-2013

Hi

 

NO,using MMCM or PLL to generate the reference clock to transceivers is not recommended.

 

http://www.xilinx.com/support/answers/53500.html

 

You should use a high quality clock source directly driving this and the VC707 user guide gives you more details on this clocking options for the transceivers.

 

Regards,

Satish

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Participant
Participant
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Registered: ‎01-30-2017

Specifically you need

 

IOSTANDARD => "LVDS

 

or

 

.IDOSTANDARD("LVDS")

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