01-29-2018 04:33 PM
I have a board with a Zynq 007S whose IO's connect to another board that powers up before my Zynq. Will it harm the Zynq if the IO's on the Zynq are being driven high by the other board before the power to the Zynq comes up?
01-30-2018 07:08 AM
You must observe the absolute maximum ratings in Table 1 of the data sheet. Failure to do so will likely destroy the device.
No more than 100 mA should be forced into any IO bank, no more than 200 mA through all IO.
That said, you will power up the IO bank from driving them from a powered device (IO bank needs less than 2mA) through the device IO protection diodes. This may or may not affect your application. It will not damage the device.
01-30-2018 07:56 AM
Just to clarify...it will not harm the Zynq if external devices are asserting high level signals into the IO's/MIO's during the Zynq's power up sequence...as long as that current is below the maximum listed in the datasheet?
Also, is there any danger of a latchup condition if I allow this to happen?
Lastly, are there any other known adverse effects that could result from allowing this to happen?
We are considering making design changes to our circuit boards that would prevent this condition, but we don't want to spend the time/money if it's not necessary.
01-30-2018 08:25 AM
Read the original answer: it is all there. Table 1 abs Max + latch up avoidance requires less than 100 mA in any bank, less than 200 mA for entire device.
Personally, I would NOT depend on the internal protection diodes, but add my own protection (a 1 A 3.3v zener handles ~ 10 A transient, for example).
Why? Long cables store a lot of charge. Connecting them can create voltages and currents well in excess of the Abs Max numbers (V=L di/dt, ESD from handling, etc.). Long transmission lines are used to create pulses of current or voltages used in destructive testing, so do not design that into your system!
Whenever you must connect two boards by a (long) cable, you have many opportunities to fail: ESD, RFI, EMI, Latch-up, signal integrity issues (reflections, impedance miss-match).
So, yes, you need to look at all of the above, and not 'just' latch up. Damage is one issue, working at all is the other.
01-31-2018 10:48 AM
Thanks for the additional information. I have two boards that mate together using a 100-pin board to board connector, so I'm not concerned about transients due to long cable lengths. I'm more concerned about the statement, "Damage is one issue, working at all is the other." The board with the Zynq IC uses a Power Management IC to properly sequence the various voltages to the device. So, to be honest, I'm still confused as to whether the application of an external signal before the Zynq powers up will prevent it from functioning properly. I understand that it won't damage the device.
01-31-2018 11:00 AM
The concern I would have is how are the designs (software + programmable logic RTL) are synchronized? Does the device once powered attempt to communicate with the other board, and wait until both boards are working before continuing?
What happens to the application on the board running if the other is powered down? Does it 'cash' or realize it should go back to waiting? Do they inform the user?
At the application level, there is some expectation of doing something useful, so being able to deal with one or the other boards losing power, or re-powering is probably something to consider.
Short cables may still be a signal integrity issue (impedance miss-match, reflections, data corruption), so I would also do signal integrity simulations to verify the SI (cables, pcb, io standards used).