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Visitor marcovaldo
Visitor
423 Views
Registered: ‎11-17-2018

Line 82: Signal count in unit AperturaPorta3 is connected to following multiple drivers: Driver 0: counter/count driven by output signal nc of instance Flip-Flop (counter). Driver 1: output signal cou

Hi everyone,

i'm trying to do a counter but i have this issue:

Line 82: Signal count in unit AperturaPorta3 is connected to following multiple drivers:
Driver 0: counter/count driven by output signal nc of instance Flip-Flop (counter).
Driver 1: output signal count of instance Latch (count).

i have tried to use different kinds of signal(std_logic and integer), but it gives to me always the same problem. i don't know why the signal is connected to multiple drivers.

Please help!

----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

 

entity AperturaPorta3 is
Port ( badge : in STD_LOGIC_VECTOR (1 downto 0);
col : in STD_LOGIC_VECTOR (3 downto 1);
row : in STD_LOGIC_VECTOR (4 downto 1);
clk : in STD_LOGIC;
rst : in STD_LOGIC;
door : out STD_LOGIC);
end AperturaPorta3;

architecture Behavioral of AperturaPorta3 is

type state is (idle, codeR, codeL, tryR, tryL, openedR, openedL);
signal curr_state, next_state: state;
--signal nc,count,E: std_logic :='0';
signal count,E: std_logic :='0';
--signal c: integer range 3 downto 1;
signal pw:std_logic_vector(1 downto 0);
signal input:std_logic_vector(3 downto 0);

component tastierino3 port(col : in STD_LOGIC_VECTOR (3 downto 1);
row : in STD_LOGIC_VECTOR (4 downto 1);
clk : in STD_LOGIC;
rst : in STD_LOGIC;
pw : out STD_LOGIC_VECTOR (1 downto 0));
end component;

component Contatore port ( pw : in STD_LOGIC_VECTOR (1 downto 0);
clk : in STD_LOGIC;
count : out STD_LOGIC);
end component;

begin

tastierino: tastierino3 port map(col, row,clk,rst,pw);

counter: Contatore port map (pw,clk,count);

input<=badge & pw;

current_state_register: process(clk)
begin
if rising_edge(clk) then
if rst='1' then
curr_state<=idle;
else
curr_state<=next_state;
end if;
end if;
end process;

next_state_register:process(input,curr_state,count,E)
begin
if (input="1100" or input="1101" or input="1110" or input="1111") then
E<='1';
else
E<='0';
end if;
case curr_state is
when idle=>count<='0';
if (input="00--" or E='1')then
next_state<=idle;
elsif (input="01--") then
next_state<=codeR;
elsif (input="10--") then
next_state<=codeL;
end if;
when codeR=>count<='0';
if (input="0000" or E='1' or input="0011" or input="01--")then --priorit badge sulla pw
next_state<=codeR;
elsif (input="0001") then
next_state<=tryR;
elsif (input="0010") then
next_state<=openedR;
elsif (input="10--") then
next_state<=idle;
end if;
when codeL=>count<='0';
if (input="0000" or E='1' or input="10--" or input="0011" )then --priorit badge sulla pw -> 0110
next_state<=codeL;
elsif (input="0001") then
next_state<=tryL;
elsif (input="0010") then
next_state<=openedL;
elsif (input="01--") then
next_state<=idle;
end if;
when tryR=>if ((input="0000" and count='0') or (input="0001" and count='0') or (input="0011" and count='0') or (E='1' and count='0'))then
next_state<=tryR;
elsif (input="0010" and count='0') then
next_state<=openedR;
elsif (input="01--") then
next_state<=codeR;
elsif ((input="----" and count='1')or (input="10--" and count='0')) then
next_state<=idle;
end if;
when tryL=>if ((input="0000" and count='0') or (input="0001" and count='0') or (input="0011" and count='0') or (E='1' and count='0'))then
next_state<=tryL;
elsif ((input="0010" and count='0')) then
next_state<=openedL;
elsif (input="10--") then
next_state<=codeL;
elsif ((input="----" and count='1')or (input="01--" and count='0')) then
next_state<=idle;
end if;
when openedR=>count<='0';
if (input="0---" or E='1')then
next_state<=openedR;
elsif (input="10--") then
next_state<=idle;
end if;
when openedL=>count<='0';
if (input="-0--" or E='1')then
next_state<=openedL;
elsif (input="01--") then
next_state<=idle;
end if;
when others=>if(input="----")then
next_state<=idle;
else
next_state<=idle;
end if;
end case;
end process;

outputFunction:process(curr_state)
begin
case curr_state is
when idle=>door<='0';
when codeR=>door<='0';
when codeL=>door<='0';
when tryR=>door<='0';
when tryL=>door<='0';
when openedR=>door<='1';
when openedL=>door<='1';
end case;
end process;

end Behavioral;

 --COMPONENT: numeric keypad

----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity tastierino3 is
Port ( col : in STD_LOGIC_VECTOR (3 downto 1);
row : in STD_LOGIC_VECTOR (4 downto 1);
clk : in STD_LOGIC;
rst : in STD_LOGIC;
pw : out STD_LOGIC_VECTOR (1 downto 0));
end tastierino3;

architecture Behavioral of tastierino3 is
type state is (s0,s1,s2,s3,se1,se2,se3,s4,se4);
signal curr_state, next_state: state;
signal sbagliato: std_logic;

begin

current_state_register: process(clk)
begin
if rising_edge(clk) then
if rst='1' then
curr_state<=s0;
else
curr_state<=next_state;
end if;
end if;
end process;

next_state_register:process(col,row,curr_state)
begin
if ((col="011" or col="101" or col="110" or col ="111")and(row="0011" or row="0101" or row="0110" or row="0111" or row="1001" or row="1010" or row="1011" or row="1100" or row="1101" or row="1110" or row="1111")) then
sbagliato<='1';
elsif ((col="000" or col="100" or col="010" or col="001") and (row="0000" or row="1000" or row="0100" or row="0010" or row="0001")) then
sbagliato<='0';
end if;
case curr_state is
when s0=>if((col="000" and row="0000") or (sbagliato='1')) then --/0 o E
next_state<=s0;
elsif(col="100" and row="1000") then --1
next_state<=s1;
elsif(sbagliato='0' and not((col="100" and row="1000")))then --X-{1}
next_state<=se1;
end if;
when s1=>if((col="000" and row="0000") or (sbagliato='1')) then --/0 o E
next_state<=s1;
elsif(col="010" and row="1000") then --2
next_state<=s2;
elsif(sbagliato='0' and not((col="010" and row="1000")))then --X-{2}
next_state<=se2;
end if;
when s2=>if((col="000" and row="0000") or (sbagliato='1')) then --/0 o E
next_state<=s2;
elsif(col="001" and row="1000") then --3
next_state<=s3;
elsif(sbagliato='0' and not((col="001" and row="1000")))then --X-{3}
next_state<=se3;
end if;
when s3=>if((col="000" and row="0000") or (sbagliato='1')) then --/0 o E
next_state<=s3;
elsif(col="100" and row="0100") then --4
next_state<=s4;
elsif(sbagliato='0' and not((col="100" and row="0100")))then --X-{4}
next_state<=se4;
end if;
when se1=>if((col="000" and row="0000") or (sbagliato='1')) then --/0 o E
next_state<=se1;
elsif(sbagliato='0')then --X
next_state<=se2;
end if;
when se2=>if((col="000" and row="0000") or (sbagliato='1')) then --/0 o E
next_state<=se2;
elsif(sbagliato='0')then --X
next_state<=se3;
end if;
when se3=>if((col="000" and row="0000") or (sbagliato='1')) then --/0 o E
next_state<=se3;
elsif(sbagliato='0')then --X
next_state<=se4;
end if;
when s4=>if((col="000" and row="0000") or (sbagliato='1')) then --/0 o E
next_state<=s4;
elsif(col="100" and row="1000") then
next_state<=s1;
elsif(sbagliato='0' and not((col="001" and row="1000"))) then
next_state<=se1;
end if;
when se4=>if((col="000" and row="0000") or (sbagliato='1')) then --/0 o E
next_state<=se4;
elsif(col="100" and row="1000") then
next_state<=s1;
elsif(sbagliato='0' and not((col="001" and row="1000"))) then
next_state<=se1;
end if;
end case;
end process;

output_function:process(curr_state)
begin
case curr_state is
when s0=>pw<="00";
when s1=>pw<="11";
when s2=>pw<="11";
when s3=>pw<="11";
when s4=>pw<="10";
when se1=>pw<="11";
when se2=>pw<="11";
when se3=>pw<="11";
when se4=>pw<="01";
end case;
end process;


end Behavioral;

  --COMPONENT: counter
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity Contatore is
Port ( pw : in STD_LOGIC_VECTOR (1 downto 0);
clk : in STD_LOGIC;
count : out STD_LOGIC);
end Contatore;

architecture Behavioral of Contatore is

signal c: integer range 3 downto 1;
signal nc: std_logic :='0';

begin

process(pw,c,clk)
begin
if rising_edge(clk) then
if(pw="01") then
c<=c+1;
if c=3 then
nc<='1';
else
nc<='0';
end if;
elsif (pw="10") then
c<=1;
nc<='0';
else
c<=c+0;
nc<='0';
end if;

end if;
end process;
count<=nc;


end Behavioral;

 

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4 Replies
407 Views
Registered: ‎06-21-2017

Re: Line 82: Signal count in unit AperturaPorta3 is connected to following multiple drivers: Driver 0: counter/count driven by output signal nc of instance Flip-Flop (counter). Driver 1: output signal

Your count sigbnel is driven by the next_state_register process as well as the line count<=nc; in the Contatore component.  These are the same signal and may only have one driver.  In hardware "count" will be a route in an FPGA and may only be driven by one LUT or one register.

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Visitor marcovaldo
Visitor
394 Views
Registered: ‎11-17-2018

Re: Line 82: Signal count in unit AperturaPorta3 is connected to following multiple drivers: Driver 0: counter/count driven by output signal nc of instance Flip-Flop (counter). Driver 1: output signal

Now i have this problem:

WARNING:Xst:3002 - This design contains one or more registers/latches that are directly
incompatible with the Automotive Spartan6 architecture. The two primary causes of this is
either a register or latch described with both an asynchronous set and
asynchronous reset, or a register or latch described with an asynchronous
set or reset which however has an initialization value of the opposite
polarity (i.e. asynchronous reset with an initialization value of 1).
While this circuit can be built, it creates a sub-optimal implementation
in terms of area, power and performance. For a more optimal implementation
Xilinx highly recommends one of the following:

1) Remove either the set or reset from all registers and latches
if not needed for required functionality
2) Modify the code in order to produce a synchronous set
and/or reset (both is preferred)
3) Ensure all registers have the same initialization value as the
described asynchronous set or reset polarity
4) Use the -async_to_sync option to transform the asynchronous
set/reset to synchronous operation
(timing simulation highly recommended when using this option)

 

i understand that tastierino3's module has got any latch, infact the synthesis of main module generates 8 latch

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378 Views
Registered: ‎06-21-2017

Re: Line 82: Signal count in unit AperturaPorta3 is connected to following multiple drivers: Driver 0: counter/count driven by output signal nc of instance Flip-Flop (counter). Driver 1: output signal

You don't show your new code and you don't twll us which signal the warning is complaining about.  My guess is E.  It is explicitly initialized to '0' and the synthesis may be ANDing the two MSBs of "input" to produce an asynchronous set.  That's just a guess.  The warning message gives several suggestions to fix this.

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Visitor marcovaldo
Visitor
359 Views
Registered: ‎11-17-2018

Re: Line 82: Signal count in unit AperturaPorta3 is connected to following multiple drivers: Driver 0: counter/count driven by output signal nc of instance Flip-Flop (counter). Driver 1: output signal

questo è il codice

-------------------------------------------------- --------------------------------
- Azienda:
- Ingegnere:
-
- Data di creazione: 10:19 : 27 02/09/2019
- Nome design:
- Nome modulo: tastierino3 - Comportamentale
- Nome progetto:
- Dispositivi target:
- Versioni strumento:
- Descrizione:
-
- Dipendenze:
-
- Revisione :
- Revisione 0.01 - File creato
- Commenti aggiuntivi:
-
----------------------------------- -----------------------------------------------
libreria IEEE;
utilizzare IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity tastierino3 is
Port ( col : in STD_LOGIC_VECTOR (3 downto 1);
row : in STD_LOGIC_VECTOR (4 downto 1);
clk : in STD_LOGIC;
rst : in STD_LOGIC;
pw : out STD_LOGIC_VECTOR (1 downto 0));
end tastierino3;

architecture Behavioral of tastierino3 is
type state is (s0,s1,s2,s3,se1,se2,se3,s4,se4);
signal curr_state, next_state: state;
signal sbagliato: std_logic;

begin
current_state_register: process(clk)
begin
if rising_edge(clk) then
if rst='1' then
curr_state<=s0;
else
curr_state<=next_state;
end if;
end if;
end process;

next_state_register:process(col,row,curr_state)
begin
if ((col="011" or col="101" or col="110" or col="111")and(row="0011" or row="0101" or row="0110" or row="0111" or row="1001" or row="1010" or row="1011" or row="1100" or row="1101" or row="1110" or row="1111")) then
sbagliato<='1';
elsif ((col="000" or col="100" or col="010" or col="001") and (row="0000" or row="1000" or row="0100" or row="0010" or row="0001")) then
sbagliato<='0';
end if;
case curr_state is
when s0=>if((col="000" and row="0000") or (sbagliato='1')) then --/0 o E
next_state<=s0;
elsif(col="100" and row="1000") then --1
next_state<=s1;
elsif(sbagliato='0' and not((col="100" and row="1000")))then --X-{1}
next_state<=se1;
end if;
when s1=>if((col="000" and row="0000") or (sbagliato='1')) then --/0 o E
next_state<=s1;
elsif(col="010" and row="1000") then --2
next_state<=s2;
elsif(sbagliato='0' and not((col="010" and row="1000")))then --X-{2}
next_state<=se2;
end if;
when s2=>if((col="000" and row="0000") or (sbagliato='1')) then --/0 o E
next_state<=s2;
elsif(col="001" and row="1000") then --3
next_state<=s3;
elsif(sbagliato='0' and not((col="001" and row="1000")))then --X-{3}
next_state<=se3;
end if;
when s3=>if((col="000" and row="0000") or (sbagliato='1')) then --/0 o E
next_state<=s3;
elsif(col="100" and row="0100") then --4
next_state<=s4;
elsif(sbagliato='0' and not((col="100" and row="0100")))then --X-{4}
next_state<=se4;
end if;
when se1=>if((col="000" and row="0000") or (sbagliato='1')) then --/0 o E
next_state<=se1;
elsif(sbagliato='0')then --X
next_state<=se2;
end if;
when se2=>if((col="000" and row="0000") or (sbagliato='1')) then --/0 o E
next_state<=se2;
elsif(sbagliato='0')then --X
next_state<=se3;
end if;
when se3=>if((col="000" and row="0000") or (sbagliato='1')) then --/0 o E
next_state<=se3;
elsif(sbagliato='0')then --X
next_state<=se4;
end if;
when s4=>if((col="000" and row="0000") or (sbagliato='1')) then --/0 o E
next_state<=s4;
elsif(col="100" and row="1000") then
next_state<=s1;
elsif(sbagliato='0' and not((col="001" and row="1000"))) then
next_state<=se1;
end if;
when se4=>if((col="000" and row="0000") or (sbagliato='1')) then --/0 o E
next_state<=se4;
elsif(col="100" and row="1000") then
next_state<=s1;
elsif(sbagliato='0' and not((col="001" and row="1000"))) then
next_state<=se1;
end if;
end case;
end process;

output_function: process (curr_state)
begin
case curr_state è
quando s0 => ​​pw <= "00";
quando s1 => pw <= "11";
quando s2 => pw <= "11";
quando s3 => pw <= "11";
quando s4 => pw <= "10";
quando se1 => pw <= "11";
quando se2 => pw <= "11";
quando se3 => pw <= "11";
quando se4 => pw <= "01";
fine caso;
fine del processo;

fine comportamentale;

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