Link Training with IO DELAY for xcvu440-flga2892-1-c

[fpgalearner]

Hi,

Is there any reference design that uses link training with IO DELAY?

I saw a IDELAYE3 component in ug974 page 315

if not? can anybody give me some idea how to implement it?

Thanks

[syedz]

@fpgalearner 

If you are looking for examples on IO DELAY then You can create high speed select IO IP and open its example design. 

https://www.xilinx.com/support/documentation/ip_documentation/high_speed_selectio_wiz/v3_5/pg188-high-speed-selectio-wiz.pdf

--Syed

[fpgalearner]

@syedz
this solution seems like source synchronous. Is there any other solution which is not source synchronous and support also smaller FPGA like artix?