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Explorer
Explorer
289 Views
Registered: ‎04-11-2016

Link Training with IO DELAY for xcvu440-flga2892-1-c

Hi,

Is there any reference design that uses link training with IO DELAY?

I saw a IDELAYE3 component in ug974 page 315

if not? can anybody give me some idea how to implement it?

Thanks

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2 Replies
Moderator
Moderator
241 Views
Registered: ‎01-16-2013

Re: Link Training with IO DELAY for xcvu440-flga2892-1-c

@fpgalearner 

 

If you are looking for examples on IO DELAY then You can create high speed select IO IP and open its example design. 

https://www.xilinx.com/support/documentation/ip_documentation/high_speed_selectio_wiz/v3_5/pg188-high-speed-selectio-wiz.pdf

image.png

 

--Syed

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Did you check our new quick reference timing closure guide (UG1292)?
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Explorer
Explorer
219 Views
Registered: ‎04-11-2016

Re: Link Training with IO DELAY for xcvu440-flga2892-1-c

@syedz
this solution seems like source synchronous. Is there any other solution which is not source synchronous and support also smaller FPGA like artix?
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