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Observer tlapauw
Observer
1,892 Views
Registered: ‎04-30-2018

Locking the PLL on lower freqency - Resetting the PLL counters

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Hi

 

So for a project, I need the PLL to lock on a frequency (Fin) below the minimum input frequency of the PLL block which is 10Mhz. To do this I would put an external frequency multiplier outside of the FPGA to get the PLL input frequency (Fmult) above the lower limit. As such the PLL will be able to lock on the higher freqency.

 

In the end the PLL will be used to generate the same output frequency(Fout) as Fin, but this clock needs a deterministic phase relation between Fin and Fout. Since the PLL will be able to lock on any edge of Fmult, the phase relation will be random on each time of lock.

 

To remedy this, the counters of the PLL should be reset once at the rising edge of Fin after lock has occurred. This way the counters will start counting up from zero starting at the rising edge of the clock to which it should be synchronous to(Fin).

Now, some things that I could not clear up from the datasheets. Does the PLL lose lock when it is reset using the Asynchronous reset input? Does this reset the counters of the PLL? Is there another way to reset the counters?

Or is there another way to use the PLL to lock on freqencies below 10Mhz? (Preferably on frequencies from 0.5Mhz (or 1Mhz) to 100Mhz)

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Mentor jmcclusk
Mentor
1,858 Views
Registered: ‎02-24-2014

Re: Locking the PLL on lower freqency - Resetting the PLL counters

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There's another way to do this, rather than using an external frequency multiplier.    Assuming that your external frequency is relatively stable, and not modulated, or doing some sort of spread spectrum,  you can construct a 2nd order digital phase locked loop using the MMCM dynamic phase shift capability.    In order to do this,  you need to drive the MMCM primary clock input with a fixed frequency (say, around 100 to 200 MHz), and then construct a synthesized frequency as close as possible to your target input frequency (using the MMCM dividers and external logic).   Then you use a digital phase detector to determine the phase difference between your input clock (at .5 or 1.0 MHz) and the synthesized clock, using that phase difference as input to a 2nd order digital low pass filter (a couple of accumulators) which drives an accumulator acting as an oscillator that provides phase shift pulses to the MMCM dynamic phase shift input.    The phase shift pulses will be either positive or negative, depending on the sign of the phase shift detected.   

 

I did this a few years ago, locking the MMCM to a 15 KHz video horizontal sync signal, and it worked.   The output phase noise was not outstanding, but it was acceptable.   The trick to getting high time resolution on the phase detector is to use quadrature sampling on the ISERDES input, using 2 clocks at 400 MHz with a 90 degree phase difference, so the actual sample resolution is at an equivalent 1600 MHz.  XAPP523 shows how to boost the sample rate up to 5 GHz, which is equal to 200 ps timing resolution!  

Don't forget to close a thread when possible by accepting a post as a solution.

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Mentor jmcclusk
Mentor
1,859 Views
Registered: ‎02-24-2014

Re: Locking the PLL on lower freqency - Resetting the PLL counters

Jump to solution

There's another way to do this, rather than using an external frequency multiplier.    Assuming that your external frequency is relatively stable, and not modulated, or doing some sort of spread spectrum,  you can construct a 2nd order digital phase locked loop using the MMCM dynamic phase shift capability.    In order to do this,  you need to drive the MMCM primary clock input with a fixed frequency (say, around 100 to 200 MHz), and then construct a synthesized frequency as close as possible to your target input frequency (using the MMCM dividers and external logic).   Then you use a digital phase detector to determine the phase difference between your input clock (at .5 or 1.0 MHz) and the synthesized clock, using that phase difference as input to a 2nd order digital low pass filter (a couple of accumulators) which drives an accumulator acting as an oscillator that provides phase shift pulses to the MMCM dynamic phase shift input.    The phase shift pulses will be either positive or negative, depending on the sign of the phase shift detected.   

 

I did this a few years ago, locking the MMCM to a 15 KHz video horizontal sync signal, and it worked.   The output phase noise was not outstanding, but it was acceptable.   The trick to getting high time resolution on the phase detector is to use quadrature sampling on the ISERDES input, using 2 clocks at 400 MHz with a 90 degree phase difference, so the actual sample resolution is at an equivalent 1600 MHz.  XAPP523 shows how to boost the sample rate up to 5 GHz, which is equal to 200 ps timing resolution!  

Don't forget to close a thread when possible by accepting a post as a solution.

View solution in original post

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Observer tlapauw
Observer
1,604 Views
Registered: ‎04-30-2018

Re: Locking the PLL on lower freqency - Resetting the PLL counters

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Thank you for the answer. 

 

It seems like a rather complex and perhaps not easy to get it right. Because this is currently not a priority in development, so it might take a while before I will try it out.

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