cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
Highlighted
Adventurer
Adventurer
5,833 Views
Registered: ‎04-14-2016

LogiCORE IP 7 Series optional ports

Jump to solution

Hello,

 

I would like to access the CPLLLOCK port, but I didn't find it in the list of optional ports of LogiCORE IP 7 Series FPGAs Transeivers (pg168). The QPLLLOCK port is available, but how can I get the CPLLLOCK port (I need to know when CPLL has locked after PLL switch). Is it possible to remove the read-only attribute from the core in order to access these ports or is there another way?

I use the option with shared logic, but CPLLLOCK is not part of it.

In general, why does ug476 descibes a lot of ports which I cannot access or can they be accessed without the IP?

 

Thanks

0 Kudos
1 Solution

Accepted Solutions
Highlighted
Adventurer
Adventurer
10,662 Views
Registered: ‎04-14-2016

Hello, thank you. Your answer is working in so far, that I get the CPLLLOCK but no QPLLLOCK. But through setting QPLL for RX and CPLL for TX it worked for me. A bit strange how to access these ports (QPLLPD and CPLLPD are optional ports selectable in the wizard, but for what use is QPLLPD and CPLLPD in terms of switching between PLLs without the clock lock signals?).

View solution in original post

0 Kudos
4 Replies
Highlighted
Moderator
Moderator
5,816 Views
Registered: ‎02-16-2010
Which PLL is selected in "Line rate and refclk selection" of the GUI? Check if it is CPLL.

If line rate is more than 6.6Gbps, QPLL will be selected.
------------------------------------------------------------------------------
Don't forget to reply, give kudo and accept as solution
------------------------------------------------------------------------------
0 Kudos
Highlighted
Adventurer
Adventurer
5,804 Views
Registered: ‎04-14-2016

I selected QPLL in the wizard, but I would like to switch between QPLL/CPLL dynamically, so I need CPLLLOCK. I do the switching with a FSM as described in the transceiver user guide (ug476 I think). So my question was how can I get access to CPLLLOCK, because I need also QPLLLOCK (which I have at the moment).

0 Kudos
Highlighted
Moderator
Moderator
5,565 Views
Registered: ‎02-16-2010
Generate the core with CPLL and set "shared logic in example". You should be able to find both QPLLLOCK/CPLLLOCK ports.

As I see, PLL lock ports are not present in the optional ports section.
------------------------------------------------------------------------------
Don't forget to reply, give kudo and accept as solution
------------------------------------------------------------------------------
Highlighted
Adventurer
Adventurer
10,663 Views
Registered: ‎04-14-2016

Hello, thank you. Your answer is working in so far, that I get the CPLLLOCK but no QPLLLOCK. But through setting QPLL for RX and CPLL for TX it worked for me. A bit strange how to access these ports (QPLLPD and CPLLPD are optional ports selectable in the wizard, but for what use is QPLLPD and CPLLPD in terms of switching between PLLs without the clock lock signals?).

View solution in original post

0 Kudos