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vian
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Registered: ‎09-03-2020

Looking for smallest verlilog code and small xdc file

 

Hi I am looking for a small test.v and  

 

Can somehelp me with small example test.v 

1) test.v should be tristate buffer connected to a output port

2 Relevant xdc file

3) How to create RPM for that

read_verilog my.v

synth_design -name test -top top

opt_design

read_xdc myt.xdc

place_design

route_design

save_project_as -force project/test

Example SchematicExample Schematic

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