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Observer
Observer
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Registered: ‎07-24-2015

MGT CLOCK distribution

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HI: I have a little problem.There are two 1xlane SRIOs on the same MGT bank of xc7vx690T, but only a pair of differential clock on the same bank.The working platform is vivado 2014.4. The input clock of SRIO  goes  through IBUFDS_GTE2, BUFG,MMCM and so on,which is encapsulated in the SRIO core and can not be changed. but now I need two pairs of differential clock.Could you give me some suggestions ,thank you !

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Xilinx Employee
Xilinx Employee
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Registered: ‎01-03-2008

Re: MGT CLOCK distribution

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> Do you think the solution is to share COMMON block? thank you.

 

You either need to share the COMMON block or eliminate it.  There are no other choices.

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Community Manager
Community Manager
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Registered: ‎07-23-2012

Re: MGT CLOCK distribution

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You can make use of shared logic to drive the GT reference clock from one SRIO core (master-> Shared logic is present in the core) to another.

Please refer to chapter 3 of PG007 for details on shared logic.
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Observer
Observer
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Registered: ‎07-24-2015

Re: MGT CLOCK distribution

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When I share logic resource(only  clock), there are some problems,whether the Reset logic and GT COMMON block need to be shared.the problems are:

 

[Place 30-510] Unroutable Placement! A GTHE_COMMON / GTHE_CHANNEL clock component pair is not placed in a routable site pair. The GTHE_COMMON component can use the dedicated path between the GTHE_COMMON and the GTHE_CHANNEL if both are placed in the same clock region. If this sub optimal condition is acceptable for this design, you may use the CLOCK_DEDICATED_ROUTE constraint in the .xdc file to demote this message to a WARNING. However, the use of this override is highly discouraged. These examples can be used directly in the .xdc file to override this clock rule.
< set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets V7_SRIO_GTH_4x_send/trans_fpga2srio1/U_srio_example/srio_support_inst/v7_gthe2_common_inst/O1] >

V7_SRIO_GTH_4x_send/trans_fpga2srio1/U_srio_example/srio_support_inst/v7_gthe2_common_inst/gthe2_common_i (GTHE2_COMMON.QPLLOUTCLK) is provisionally placed by clockplacer on GTHE2_COMMON_X1Y8
V7_SRIO_GTH_4x_send/trans_fpga2srio1/U_srio_example/srio_support_inst/srio_gen2_0_inst/inst/srio_gt_wrapper_inst/gtwizard_0_init_inst/gtwizard_0_i/gt0_gtwizard_0_i/gthe2_i (GTHE2_CHANNEL.QPLLCLK) is locked to GTHE2_CHANNEL_X1Y31

The above error could possibly be related to other connected instances. Following is a list of
all the related clock rules and their respective instances.

Clock Rule: rule_gthcommon_gthchannel
Status: PASS
Rule Description: A GTHCommon driving a GTHChannel must both be in the same clock region
V7_SRIO_GTH_4x_rcv/trans_fpga2srio3/U_srio_example/srio_support_inst/v7_gthe2_common_inst/gthe2_common_i (GTHE2_COMMON.QPLLOUTCLK) is provisionally placed by clockplacer on GTHE2_COMMON_X1Y7
V7_SRIO_GTH_4x_rcv/trans_fpga2srio3/U_srio_example/srio_support_inst/srio_gen2_1_inst/inst/srio_gt_wrapper_inst/gtwizard_0_init_inst/gtwizard_0_i/gt0_gtwizard_0_i/gthe2_i (GTHE2_CHANNEL.QPLLCLK) is locked to GTHE2_CHANNEL_X1Y30

Clock Rule: rule_bufds_bufg
Status: PASS
Rule Description: A BUFDS driving a BUFG must be placed on the same half side (top/bottom) of the device
srio_clk_inst/u_refclk_ibufds (IBUFDS_GTE2.O) is locked to IBUFDS_GTE2_X1Y14
srio_clk_inst/refclk_bufg_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y31

Clock Rule: rule_bufds_gthchannel_intelligent_pin
Status: PASS
Rule Description: A BUFDS driving a GTHChannel must both be placed in the same or adjacent clock region
(top/bottom)
srio_clk_inst/u_refclk_ibufds (IBUFDS_GTE2.O) is locked to IBUFDS_GTE2_X1Y14
V7_SRIO_GTH_4x_send/trans_fpga2srio1/U_srio_example/srio_support_inst/srio_gen2_0_inst/inst/srio_gt_wrapper_inst/gtwizard_0_init_inst/gtwizard_0_i/gt0_gtwizard_0_i/gthe2_i (GTHE2_CHANNEL.GTREFCLK0) is locked to GTHE2_CHANNEL_X1Y31
V7_SRIO_GTH_4x_rcv/trans_fpga2srio3/U_srio_example/srio_support_inst/srio_gen2_1_inst/inst/srio_gt_wrapper_inst/gtwizard_0_init_inst/gtwizard_0_i/gt0_gtwizard_0_i/gthe2_i (GTHE2_CHANNEL.GTREFCLK0) is locked to GTHE2_CHANNEL_X1Y30

Clock Rule: rule_bufds_gthcommon_intelligent_pin
Status: PASS
Rule Description: A BUFDS driving a GTHCommon must both be placed in the same or adjacent clock region
(top/bottom)
srio_clk_inst/u_refclk_ibufds (IBUFDS_GTE2.O) is locked to IBUFDS_GTE2_X1Y14
V7_SRIO_GTH_4x_send/trans_fpga2srio1/U_srio_example/srio_support_inst/v7_gthe2_common_inst/gthe2_common_i (GTHE2_COMMON.GTREFCLK0) is provisionally placed by clockplacer on GTHE2_COMMON_X1Y8
and V7_SRIO_GTH_4x_rcv/trans_fpga2srio3/U_srio_example/srio_support_inst/v7_gthe2_common_inst/gthe2_common_i (GTHE2_COMMON.GTREFCLK0) is provisionally placed by clockplacer on GTHE2_COMMON_X1Y7

 

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Xilinx Employee
Xilinx Employee
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Registered: ‎02-06-2013

Re: MGT CLOCK distribution

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Hi

 

Did you generate the 2nd core with shared logic in example design option?

Regards,

Satish

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Observer
Observer
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Registered: ‎07-24-2015

Re: MGT CLOCK distribution

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YES,I use two SRIO cores, but the shared logic resource which  is used is only clock.

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Xilinx Employee
Xilinx Employee
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Registered: ‎01-03-2008

Re: MGT CLOCK distribution

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It looks like you have the "send" core and the "rcv" core placed in the same Quad as the "send" channel is reported as placed in GTHE2_CHANNEL_X1Y31 (117-3) and the "rcv" channel placed in GTHE2_CHANNEL_X1Y30 (117-2).  Since there is only one COMMON block per quad your design is not possible.

 

Hopefully, this is not at the PCB stage and you can implement the required changes to move the two channels to different Quads.  If you already have a PCB then you will need either need to remove the requirement for the COMMON block by using the Channel PLLs or rewrite the HDL to share the COMMON block between the two cores.

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Observer
Observer
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Registered: ‎07-24-2015

Re: MGT CLOCK distribution

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OK,I will try it.

This is my top level module

捕获.PNG

the module srio_gen2_0 and  srio_gen2_0 share  clock.

this is my pin configuration.

捕获1.PNG

The third one is my PCB.

2015-08-17_222458.png

Do you think the solution is to share COMMON block? thank you.

 

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Xilinx Employee
Xilinx Employee
12,145 Views
Registered: ‎01-03-2008

Re: MGT CLOCK distribution

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> Do you think the solution is to share COMMON block? thank you.

 

You either need to share the COMMON block or eliminate it.  There are no other choices.

------Have you tried typing your question into Google? If not you should before posting.
Too many results? Try adding site:www.xilinx.com

View solution in original post